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PDF PI6C671E Data sheet ( Hoja de datos )
| Número de pieza | PI6C671E | |
| Descripción | Clock Generator | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6C671E
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Clock Generator for Pentium Notebooks
with I2C and SDRAM Support
Features
• Supports Pentium or Pentium II CPUs
• Spread spectrum capability reduces EMI
• Low power consumption
• Four CPU Clocks with Vddq2 of 3.3V or 2.5V
• Seven PCI synchronous clocks (3.3V)
• One IOAPIC Clock @14.31818 MHz
with VDDQ1 of 3.3V or 2.5V (power from pin 46)
• Two 48/24 MHz clocks (3.3V)
• Six/eight SDRAM clocks (3.3V)
• Three Ref. Clocks @14.31818 MHz (3.3V)
• Ref. 14.31818 MHz crystal oscillator input
• Separate 66/60# MHz select pin
• Separate power management MODE control pin
• I2C 2-Wire Serial Interface
• 48-pin SSOP and TSSOP Packages
Description
The PI6C671E is a mixed-voltage clock generator designed to
provide all timing signals for Intel Pentium/Pentium II based
motherboards. It provides four CPU, seven PCI, and up to eight
SDRAM clocks. Additionally, three reference clocks (same fre-
quency as the crystal) and two selectable 24/48 MHz clocks are
available.
Pericom design improvements resulted in a low-power device. A
special spread-spectrum feature may be enabled to minimize EMI.
The two-wire I2C serial interface can be used to reduce circuit
noise and power consumption. I2C control lets you enable/disable
each clock output driver, change CPU frequencies, and select 24
or 48 MHz outputs.
A power-down function (pin 44) puts the whole system in a low-
power mode by stopping the crystal oscillator and both PLLs. CPU
and PCI clocks may also be stopped by the “CPU_STOP#” (pin 27),
and “PCI_STOP#” (pin 26) functions.
Note: Purchase of I2C components from Pericom conveys a license
to use them in an I2C system as defined by Philips.
Block Diagram
X IN
X OUT
REF
OSC
SEL
PLL1
PLL2
÷2
*KBBAHI
V DDQ 1
V DDQ 2
V DDQ 3
3
REF0,1,2
IOAPIC0
4
CPUCLK0-3
Up to 8
SDRAM0-7
6
PCICLK0-5
PCICLK_F
48/24 MHz
48/24 MHz
All trademarks are of their respective companies.
Pin Configuration
REF1 1
REF0 2
V SS 3
Xin 4
Xout 5
MODE 6
V DDQ 3 7
PCICLK_F 8
PCICLK0 9
V SS 10
PCICLK1 11
PCICLK2 12
PCICLK3 13
PCICLK4 14
V DDQ 3 15
PCICLK5 16
V SS 17
SEL66/60# 18
SDATA 19
SDCLK 20
V DDQ 3 21
48/24MHz 22
48/24MHz 23
V SS 24
48
47
46
45
44
43
42
41
40
48-Pin 39
A, V 38
37
36
35
34
33
32
31
30
29
28
27
26
25
V DD
REF2
V DDQ 1
IOAPIC0
PWR_DWN#
V SS
CPUCLK0
CPUCLK1
V DDQ 2
CPUCLK2
CPUCLK3
V SS
SDRAM0
SDRAM1
V DDQ 3
SDRAM2
SDRAM3
V SS
SDRAM4
SDRAM5
V DDQ 3
SDRAM6/CPU_STOP#
SDRAM7/PCI_STOP#
V DD
385
PS8116D 10/07/97
Free Datasheet http://www.Datasheet4U.com
1 page  
PI6C671E
Clock Generator for Pentium Notebooks
2
with I C and SDRAM Support1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Byte 7: Frequency Control
Bit @ Power up
Description
DC Specifications
Absolute Maximum DC Power Supply
1
7X
6X
5X
4X
3X
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Symbol Supply Voltage
VDDQ3
VDD
VDDQ2
VDDQ1
3.3V Core & I/O
3.3V Core
2.5/3.3V I/O
2.5/3.3V I/O
Min. Max. Units
-0.5 4.6
-0.5 4.6
-0.5 4.6
V
-0.5 4.6
2
3
21
FSEL2
11
01
FSEL1
FSEL0
FSEL2 FSEL1 FSEL0
Frequency
0 0 0 (Reserved)
0 0 1 (Reserved)
0 1 0 (Reserved)
0 1 1 33 MHz
1 0 0 50 MHz
10
1 55 MHz
1 1 0 60 MHz
1 1 1 From SEL66/60# pin
DC Operating Requirements
(VDD, VDDQ3 = 3.3V ±5%, VDDQ2 = 2.5V ±5%, TA = 0 to 70°C)
Symbol Parameter
Condition
Min. Typ. Max. Units
VOH2
2.5V Output
High Voltage
IOH = -1mA
2.1
VOH3
VOL2
3.3V Output
High Voltage
2.5V Output
Low Voltage
IOH = -1mA
IOL = 1mA
2.4
V
0.4
VOL3
3.3V Output
Low Voltage
IOL = 1mA
0.4
Dynamic
IDD Supply
Current
66MHz
Unloaded
Outputs
55 70 mA
IPD
Power Down
Supply
Current
PWR_DWN# = 0
MODE = Float (High)
14 20 µA
4
5
6
7
8
9
Note: Typical values are at room temperature
AC Timing
Symbol
tRF
tJITTER
Duty Cycle
tHSKW
tHSKSD
tPKPS
tPSKW
Parameter
Host CLK rise/fall time, 0.4V - 2.0V
Host CLK Jitter
Measured the rising edge CLKs at 1.25V for the
2.5V clocks and at 1.5V for the 3.3V clocks
Host Bus CLK skew
Host to SDRAM
PCI CLK period stability
PCI Bus CLK skew
Min.
0.4
Max.
1.6
250
Unit
ns
ps
45 55 %
250
500
ps
500
500
10
11
12
13
14
15
tHPOFFSET Host to PCI Clock Offset
tSTB
CLK Stabilization at power-up
1.0 4.0 ns
3 ms
389
PS8116D 10/07/97
Free Datasheet http://www.Datasheet4U.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PI6C671E.PDF ] | |
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