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PDF HEF4093B Data sheet ( Hoja de datos )
| Número de pieza | HEF4093B | |
| Descripción | Quad 2-input NAND Schmitt trigger | |
| Fabricantes | NXP Semiconductors | |
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HEF4093B
Quad 2-input NAND Schmitt trigger
Rev. 9 — 15 December 2015
Product data sheet
1. General description
The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit.
The gate switches at different points for positive-going and negative-going signals. The
difference between the positive voltage (VT+) and the negative voltage (VT) is defined as
hysteresis voltage (VH).
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Schmitt trigger input discrimination
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from40 C to +85 C and 40 C to +125 C
Complies with JEDEC standard JESD 13-B
3. Applications
Wave and pulse shapers
Astable multivibrators
Monostable multivibrators
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +125 C
Type number
Package
Name
Description
HEF4093BT
SO14
plastic small outline package; 14 leads; body width 3.9 mm
Version
SOT108-1
1 page  
NXP Semiconductors
HEF4093B
Quad 2-input NAND Schmitt trigger
11. Dynamic characteristics
Table 7. Dynamic characteristics
Tamb = 25 C; CL = 50 pF; tr = tf 20 ns; wave forms see Figure 4; test circuit see Figure 5; unless otherwise specified.
Symbol Parameter
Conditions VDD
Extrapolation formula[1] Min Typ Max Unit
tPHL HIGH to LOW
propagation delay
nA or nB to nY 5 V
10 V
63 ns + (0.55 ns/pF)CL
29 ns + (0.23 ns/pF)CL
- 90 185 ns
- 40 80 ns
15 V
22 ns + (0.16 ns/pF)CL
- 30 60 ns
tPLH LOW to HIGH
propagation delay
nA or nB to nY 5 V
10 V
58 ns + (0.55 ns/pF)CL
29 ns + (0.23 ns/pF)CL
- 85 170 ns
- 40 80 ns
15 V
22 ns + (0.16 ns/pF)CL
- 30 60 ns
tTHL HIGH to LOW output nY to LOW 5 V
transition time
10 V
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
- 60 120 ns
- 30 60 ns
15 V
6 ns + (0.28 ns/pF)CL
- 20 40 ns
tTLH LOW to HIGH output nA or nB to 5 V
transition time
HIGH
10 V
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
- 60 120 ns
- 30 60 ns
15 V
6 ns + (0.28 ns/pF)CL
- 20 40 ns
[1] Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).
Table 8. Dynamic power dissipation
VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD Typical formula
PD dynamic power
5 V PD = 1300 fi + (fo CL) VDD2 (W)
dissipation
10 V PD = 6400 fi + (fo CL) VDD2 (W)
15 V PD = 18700 fi + (fo CL) VDD2 (W)
where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
(fo CL) = sum of the outputs;
VDD = supply voltage in V.
HEF4093B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 14
5 Page 
NXP Semiconductors
HEF4093B
Quad 2-input NAND Schmitt trigger
16. Abbreviations
Table 12. Abbreviations
Acronym
Description
DUT
Device Under Test
17. Revision history
Table 13. Revision history
Document ID
Release date Data sheet status
Change notice
HEF4093B v.9
Modifications:
20151215
Product data sheet
-
• Type number HEF4093BP (SOT27-1) removed.
HEF4093B v.8
Modifications:
HEF4093B v.7
20111121
Product data sheet
-
• Table 6: IOH minimum values changed to maximum
20100901
Product data sheet
-
HEF4093B v.6
20091202
Product data sheet
-
HEF4093B v.5
20090728
Product data sheet
-
HEF4093B v.4
20080612
Product data sheet
-
HEF4093B_CNV v.3
19950101
Product specification
-
HEF4093B_CNV v.2
19950101
Product specification
-
Supersedes
HEF4093B v.8
HEF4093B v.7
HEF4093B v.6
HEF4093B v.5
HEF4093B v.4
HEF4093B_CNV v.3
HEF4093B_CNV v.2
-
HEF4093B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 14
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