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PDF HEF4052B Data sheet ( Hoja de datos )
| Número de pieza | HEF4052B | |
| Descripción | Dual 4-channel analogue multiplexer/demultiplexer | |
| Fabricantes | NXP Semiconductors | |
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HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
Rev. 10 — 25 March 2016
Product data sheet
1. General description
The HEF4052B is a dual 4-channel analog multiplexer/demultiplexer with common
channel select logic. Each multiplexer/demultiplexer has four independent inputs/outputs
(nY0 to nY3) and a common input/output (nZ). The common channel select logic includes
two select inputs (S1 and S2) and an active LOW enable input (E). Both
multiplexers/demultiplexers contain four bidirectional analog switches, each with one side
connected to an independent input/output (nY0 to nY3) and the other side connected to a
common input/output (nZ). With E LOW, one of the four switches is selected
(low-impedance ON-state) by S1 and S2. With E HIGH, all switches are in the
high-impedance OFF-state, independent of S1 and S2. If break before make is needed,
then it is necessary to use the enable input.
VDD and VSS are the supply voltage connections for the digital control inputs (S1 and S2,
and E). The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (nY0 to nY3, and
nZ) can swing between VDD as a positive limit and VEE as a negative limit. VDD VEE may
not exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For
operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically
ground). VEE and VSS are the supply voltage connections for the switches.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C and 40 C to +125 C
Complies with JEDEC standard JESD 13-B
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
1 page  
Nexperia
HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
+()%
<
<
=
<
<
(
9((
966
9''
<
<
=
<
<
6
6
DDJ
Fig 6. Pin configuration SOT109-1
+()%
<
<
=
<
<
(
9((
966
9''
<
<
=
<
<
6
6
DDN
Fig 7. Pin configuration SOT403-1
6.2 Pin description
Table 2. Pin description
Symbol
E
VEE
VSS
S1, S2
1Y0, 1Y1, 1Y2, 1Y3, 2Y0, 2Y1, 2Y2, 2Y3
1Z, 2Z
VDD
Pin
6
7
8
10, 9
12, 14, 15, 11, 1, 5, 2, 4
13, 3
16
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
independent input or output
common output or input
supply voltage
HEF4052B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 25 March 2016
© Nexperia B.V. 2017. All rights reserved
5 of 21
5 Page 
Nexperia
HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
Table 8. Dynamic characteristics …continued
Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 16.
Symbol Parameter
Conditions
tPZL OFF-state to LOW
propagation delay
E to nYn, nZ; see Figure 15
11.1 Waveforms and test circuit
VDD
5V
10 V
15 V
Typ Max Unit
120 240 ns
50 100 ns
35 75 ns
9''
Q<QRUQ=
LQSXW
9((
92
W3/+
Q=RUQ<Q
RXWSXW
9((
90
90
W3+/
DDF
Measurement points are given in Table 9.
Fig 13. nYn, nZ to nZ, nYn propagation delays
9''
6QLQSXW
966
92
Q<QRUQ=
RXWSXW
9((
90
W3/+
VZLWFK2))
W3+/
VZLWFK21
VZLWFK2))
DDF
Measurement points are given in Table 9.
Fig 14. Sn to nYn, nZ propagation delays
(LQSXW
9''
966
92
Q<QRUQ=RXWSXW
/2:WR2))
2))WR/2:
9((
92
Q<QRUQ=RXWSXW
+,*+WR2))
2))WR+,*+
9((
Measurement points are given in Table 9.
Fig 15. Enable and disable times
90
W3/=
W3=/
W3+=
W3=+
VZLWFK21
VZLWFK2))
VZLWFK21
DDF
Table 9. Measurement points
Supply voltage
VDD
5 V to 15 V
Input
VM
0.5VDD
Output
VM
0.5VDD
HEF4052B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 25 March 2016
© Nexperia B.V. 2017. All rights reserved
11 of 21
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