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PDF HEF4001B Data sheet ( Hoja de datos )
| Número de pieza | HEF4001B | |
| Descripción | Quadruple 2-input NOR gate | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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HEF4001B
Quad 2-input NOR gate
Rev. 10 — 10 December 2015
Product data sheet
1. General description
The HEF4001B is a quad 2-input NOR gate. The outputs are fully buffered for the highest
noise immunity and pattern insensitivity to output impedance.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +125 C
Complies with JEDEC standard JESD 13-B
Inputs and outputs are protected against electrostatic effects
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +125 C
Type number Package
Name Description
HEF4001BT SO14 plastic small outline package; 14 leads; body width 3.9 mm
4. Functional diagram
Version
SOT108-1
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%
$
%
$
%
$
%
<
<
<
<
DDJ
Fig 1. Functional diagram
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Q%
Q<
DDJ
Fig 2. Logic diagram (one gate)
1 page  
NXP Semiconductors
HEF4001B
Quad 2-input NOR gate
10. Dynamic characteristics
Table 7. Dynamic characteristics
Tamb = 25 C; for waveforms see Figure 4; for test circuit see Figure 5; unless otherwise specified.
Symbol Parameter
Extrapolation formula[1] VDD
Min
tPHL HIGH to LOW propagation delay 33 + 0.55 CL
5V -
14 + 0.23 CL
10 V
-
12 + 0.16 CL
15 V
-
tPLH LOW to HIGH propagation delay 23 + 0.55 CL
5V -
14 + 0.23 CL
10 V
-
12 + 0.16 CL
15 V
-
tTHL HIGH to LOW output transition time 10 + 1.00 CL
5V -
9 + 0.42 CL
10 V
-
6 + 0.28 CL
15 V
-
tTLH LOW to HIGH output transition time 10 + 1.00 CL
5V -
9 + 0.42 CL
10 V
-
6 + 0.28 CL
15 V
-
Typ
60
25
20
50
25
20
60
30
20
60
30
20
Max Unit
120 ns
50 ns
40 ns
100 ns
45 ns
35 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
[1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).
Table 8. Dynamic power dissipation
VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD Typical formula
Where
PD dynamic power dissipation 5 V PD = 1100 fi + (fo CL) VDD2 (W) fi = input frequency in MHz;
10 V
15 V
PD = 5000 fi + (fo CL) VDD2 (W)
PD = 14200 fi + (fo CL) VDD2 (W)
fo = output frequency in MHz;
CL = output load capacitance in pF;
(fo CL) = sum of the outputs;
VDD = supply voltage in V.
HEF4001B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 10 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 11
5 Page 
NXP Semiconductors
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 1
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Functional description . . . . . . . . . . . . . . . . . . . 2
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Recommended operating conditions. . . . . . . . 3
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 8
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 9
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 9
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
16 Contact information. . . . . . . . . . . . . . . . . . . . . 10
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
HEF4001B
Quad 2-input NOR gate
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 10 December 2015
Document identifier: HEF4001B
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet HEF4001B.PDF ] | |
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