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PDF ATF-54143 Data sheet ( Hoja de datos )
| Número de pieza | ATF-54143 | |
| Descripción | Low Noise Enhancement Mode Pseudomorphic HEMT | |
| Fabricantes | Agilent | |
| Logotipo |  |
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Agilent ATF-54143 Low Noise
Enhancement Mode
Pseudomorphic HEMT in a
Surface Mount Plastic Package
Data Sheet
Description
Agilent Technologies’s ATF-54143
is a high dynamic range, low
noise, E-PHEMT housed in a
4-lead SC-70 (SOT-343) surface
mount plastic package.
Surface Mount Package
SOT-343
The combination of high gain, high
linearity and low noise makes the
ATF-54143 ideal for cellular/PCS
base stations, MMDS, and other
systems in the 450 MHz to 6 GHz
frequency range.
Pin Connections and
Package Marking
DRAIN
SOURCE
Features
• High linearity performance
• Enhancement Mode Technology[1]
• Low noise figure
• Excellent uniformity in product
specifications
• 800 micron gate width
• Low cost surface mount small
plastic package SOT-343 (4 lead SC-
70)
• Tape-and-Reel packaging option
available
• Lead-free option available.
Attention:
Observe precautions for
handling electrostatic
sensitive devices.
ESD Machine Model (Class A)
ESD Human Body Model (Class 1A)
Refer to Agilent Application Note A004R:
Electrostatic Discharge Damage and Control.
SOURCE
GATE
Note:
Top View. Package marking provides orientation
and identification
“4F” = Device Code
“x” = Date code character
identifies month of manufacture.
Specifications
2 GHz; 3V, 60 mA (Typ.)
• 36.2 dBm output 3rd order intercept
• 20.4 dBm output power at 1 dB
gain compression
• 0.5 dB noise figure
• 16.6 dB associated gain
Applications
• Low noise amplifier for cellular/PCS
base stations
• LNA for WLAN, WLL/RLL and
MMDS applications
• General purpose discrete E-PHEMT
for other ultra low noise applications
Note:
1. Enhancement mode technology requires
positive Vgs, thereby eliminating the need for
the negative gate voltage associated with
conventional depletion mode devices.
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1 page  
ATF-54143 Typical Performance Curves, continued
2
25°C
-40°C
85°C
1.5
1.0
0.5
0
012 3 456
FREQUENCY (GHz)
Figure 15. Fmin[2] vs. Frequency and Temp
Tuned for Max OIP3 and Fmin at 3V, 60 mA.
45
40
35
30
25
20
25°C
15 -40°C
85°C
10
012 3 456
FREQUENCY (GHz)
Figure 16. OIP3 vs. Frequency and Temp
Tuned for Max OIP3 and Fmin at 3V, 60 mA.
1.4
1.2
1.0
0.8
0.6
0.4 60 mA
40 mA
0.2 80 mA
0
01 2 3 4 5 67
FREQUENCY (GHz)
Figure 18. Fmin[1] vs. Frequency and Ids
at 3V.
21
20.5
20
19.5
19
18.5
18
17.5
17
0
25°C
-40°C
85°C
1234
FREQUENCY (GHz)
5
6
Figure 17. P1dB vs. Frequency and Temp
Tuned for Max OIP3 and Fmin at 3V, 60 mA.
ATF-54143 Reflection Coefficient Parameters tuned for Maximum Output IP3,
VDS = 3V, IDS = 60 mA
Freq
(GHz)
Γ Out_Mag.[1]
(Mag)
Γ Out_Ang.[1]
(Degrees)
OIP3
(dBm)
P1dB
(dBm)
0.9 0.017
2.0 0.026
3.9 0.013
5.8 0.025
115
-85
173
102
35.54
36.23
37.54
35.75
18.4
20.38
20.28
18.09
Note:
1. Gamma out is the reflection coefficient of the matching circuit presented to the output of the device.
Note:
1. Fmin values at 2 GHz and higher are based on
measurements while the Fmins below 2 GHz
have been extrapolated. The Fmin values are
based on a set of 16 noise figure measure-
ments made at 16 different impedances using
an ATN NP5 test system. From these
measurements a true Fmin is calculated.
Refer to the noise parameter application
section for more information.
5
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5 Page 
The values of resistors R1 and R2
are calculated with the following
formulas
R1 = Vgs (2)
Ip
BB
R2 = (Vds – Vgs) R1 (3)
Vgs p
Example Circuit
VDD = 5 V
Vds = 3V
Ids = 60 mA
Vgs = 0.59V
Choose IBB to be at least 10X the
normal expected gate leakage
current. IBB was chosen to be
2 mA for this example. Using
equations (1), (2), and (3) the
resistors are calculated as
follows
R1 = 295Ω
R2 = 1205Ω
R3 = 32.3Ω
Active Biasing
Active biasing provides a means
of keeping the quiescent bias
point constant over temperature
and constant over lot to lot
variations in device dc perfor-
mance. The advantage of the
active biasing of an enhancement
mode PHEMT versus a depletion
mode PHEMT is that a negative
power source is not required. The
techniques of active biasing an
enhancement mode device are
very similar to those used to bias
a bipolar junction transistor.
INPUT
Zo
C1
Q1
L1
L2
C2
R5
C3
R6
R7
R1
C7
Q2
C4 OUTPUT
Zo
L4
L3
C5
R4
C6
R3
R2
Vdd
Figure 2. Typical ATF-54143 LNA with
Active Biasing.
An active bias scheme is shown
in Figure 2. R1 and R2 provide a
constant voltage source at the
base of a PNP transistor at Q2.
The constant voltage at the base
of Q2 is raised by 0.7 volts at the
emitter. The constant emitter
voltage plus the regulated VDD
supply are present across resis-
tor R3. Constant voltage across
R3 provides a constant current
supply for the drain current.
Resistors R1 and R2 are used to
set the desired Vds. The com-
bined series value of these
resistors also sets the amount of
extra current consumed by the
bias network. The equations that
describe the circuit’s operation
are as follows.
VE = Vds + (Ids • R4)
R3 = VDD – VE
Ids p
VB = VE – VBE
R1
VB = R1 + R2p VDD
(1)
(2)
(3)
(4)
and rearranging equation (5)
provides the following formula
R1 =
VDD 9 (5A)
( )IBB
1 + VDD – VB p
VB
Example Circuit
VDD = 5V
Vds = 3V
Ids = 60 mA
R4 = 10Ω
VBE = 0.7 V
Equation (1) calculates the
required voltage at the emitter of
the PNP transistor based on
desired Vds and Ids through
resistor R4 to be 3.6V. Equation
(2) calculates the value of resis-
tor R3 which determines the
drain current Ids. In the example
R3 =23.3Ω. Equation (3) calcu-
lates the voltage required at the
junction of resistors R1 and R2.
This voltage plus the step-up of
the base emitter junction deter-
mines the regulated Vds. Equa-
tions (4) and (5) are solved
simultaneously to determine the
value of resistors R1 and R2. In
the example R1=1450Ω and
R2 =1050Ω. R7 is chosen to be
1kΩ. This resistor keeps a small
amount of current flowing
through Q2 to help maintain bias
stability. R6 is chosen to be
10kΩ. This value of resistance is
necessary to limit Q1 gate
current in the presence of high
RF drive level (especially when
Q1 is driven to P1dB gain com-
pression point).
VDD = IBB (R1 + R2) (5)
Rearranging equation (4)
provides the following formula
R2 = R1 (VDD – VB) (4A)
VB p
11
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| Páginas | Total 17 Páginas | |
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