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PDF ISO1H816G Data sheet ( Hoja de datos )

Número de pieza ISO1H816G
Descripción Galvanic Isolated 8 Channel High-Side Switch
Fabricantes Infineon 
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No Preview Available ! ISO1H816G Hoja de datos, Descripción, Manual

ISOFACE™
ISO1H816G
Galvanic Isolated 8 Channel High-Side Switch
Datasheet
Revision 2.3, 2013-05-16
Power Management & Multimarket
Free Datasheet http://www.datasheet-pdf.com/

1 page




ISO1H816G pdf
ISOFACE™
ISO1H816G
Pin Configuration and Functionality
1 Pin Configuration and Functionality
1.1 Pin Configuration
Pin Symbol
1 N.C.
2 VCC
3 DIS
4 CS
5 SCLK
6 SI
7 N.C.
8 N.C.
9 N.C.
10 N.C.
11 N.C.
12 N.C.
13 SO
14 DIAG
15 GNDCC
16 N.C.
17 N.C.
18 N.C.
19 GNDbb
20 N.C
21 OUT7
22 OUT7
23 OUT6
24 OUT6
25 OUT5
26 OUT5
27 OUT4
28 OUT4
29 OUT3
30 OUT3
31 OUT2
32 OUT2
33 OUT1
34 OUT1
35 OUT0
36 OUT0
TAB Vbb
Function
Not connected
Positive 3.3/5V logic supply
Output disable
Chip select
Serial Clock
Serial Data input
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Serial Data Output
Common diagnostic output for
overtemperature
Input logic ground
Not connected
Not connected
Not connected
Output driver ground
Not connected
High-side output of channel 7
High-side output of channel 7
High-side output of channel 6
High-side output of channel 6
High-side output of channel 5
High-side output of channel 5
High-side output of channel 4
High-side output of channel 4
High-side output of channel 3
High-side output of channel 3
High-side output of channel 2
High-side output of channel 2
High-side output of channel 1
High-side output of channel 1
High-side output of channel 0
High-side output of channel 0
Positive driver power supply voltage
N.C.
VCC
DIS
CS
SCLK
SI
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
SO
DIAG
GNDCC
N.C.
N.C.
N.C.
Figure 1
.
Vbb
1
2
TAB
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TAB
Vbb
Power SO-36 (430mil)
36 OUT0
35 OUT0
34 OUT1
33 OUT1
32 OUT2
31 OUT2
30 OUT3
29 OUT3
28 OUT4
27 OUT4
26 OUT5
25 OUT5
24 OUT6
23 OUT6
22 OUT7
21 OUT7
20 N.C.
19 GNDbb
Datasheet
5 Revision 2.3, 2013-05-16
Free Datasheet http://www.datasheet-pdf.com/

5 Page





ISO1H816G arduino
ISOFACE™
ISO1H816G
Functional Description
more ICs is needed. All ICs share the same clock and
chip select port of the SPI master. That is all ICs are
active and addressed simultaneously. The data out of
the µC is connected to the SI of the first IC in the line.
Each SO of an IC is connected to the SI of the next IC
in the line.
wether the transmitted data is valid or not. If four times
serial data coming from the internal registers is not
accepted the output stages are switched off until the
next valid data is received.
SPI 1
CLK
Tx a1
Tx a2
SCLK
CS
SI
SO
Output lines
SPI- Interface
IC1
SCLK
CS
SI
Output lines
SPI- Interface
µC ICn
Number of adressed ICs = n
Number of necessary control and data ports = 3
All ICs are adressed by the common chip select
Figure 10 SPI bus all ICs in a “daisy chain”
configuration
The µC feeds to data bits into the SI of IC1 (first IC in
the chain). The bits coming from the SO of IC1 are
directly shifted into the SI of the next IC. As long as the
chip select is inactive (logic high) all the IC SPIs ignore
the clock (SCLK) and input signals (SI) and all outputs
(SO) are in tristate. As long as the chip select is active
the SPI register works as a simple shift register. With
each clock signal one input is shifted into the SPI
register (SI), each bit in the shift register moves one
position further within the register, and the last bit in the
SPI shift register is shifted out of SO. This continous as
long as the chip select is active (logic low) and clock
signals are applied. The data is then only taken over to
the output buffers of each IC when the CS signal
changes to high from low and recognized as valid data
by the internal modulo counter.
3.6 Transmission Failure Detection
There is a failure detection unit integrated to ensure
also a stable functionality during the integrated
coreless transformer transmission. This unit decides
Datasheet
11
Revision 2.3, 2013-05-16
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