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PDF AK8856VN Data sheet ( Hoja de datos )
| Número de pieza | AK8856VN | |
| Descripción | NTSC/PAL Video Decoder | |
| Fabricantes | AKM | |
| Logotipo |  |
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ASAHI KASEI
[AK8856VN ]
AK8856VN
NTSC/PAL Video Decoder
General Description
The AK8856 decodes NTSC or PAL composite video signals into digital video data. The outputs are ITU-R BT.
601 level compatible Y, Cb and Cr signals. The decoded result is scaled to 601, VGA (interlaced output), CIF,
QVGA, QCIF, rotated QVGA , or rotated CIF(progressive). Information including closed caption, VBID, and WSS
are encoded in the video signal can be read out externally. The AK8856 is controlled by through an I2C interface.
Features
• NTSC-M, NTSC-4.43 / PAL- B, D, G, H, I, N, Nc, M, 60 composite signal decoding process
• 10 Bit ADC (sampling at 24.5454MHz or 27MHz)
• Integrated PGA (0dB ~ 12dB)
• Automatic color control (ACC) function
• Adaptive automatic gain control (AGC) function
• 1D or 2D YC separation
• Phase compensation for PAL
• Output interface
- ITU-R BT.656 output format (4:2:2 8-bit parallel output with EAV / SAV)
- Camera interface
- Interface with HD / VD / DVALID signals
• Closed caption decoding function (read by register setting)
• VBID (CGMS-A) decoding function (CRCC decode) (read by register setting)
• WSS decoding function (read by register setting)
• Macrovision signal detect function
• Power-down function
• 2-channel analog input selector
• I2C control compatible
• Core voltage (AVDD, DVDD) 1.65 - 1.8V
• I/O voltage (PVDD) 1.65 - 3.3V
• Package: 48 QFN or 41 BGA (see VG datasheet)
* The output that meets the ITU-R BT.656 standard according to the fineness of the input signal might not be available.
MS0522-E-00
1
2006/Dec
Free Datasheet http://www.datasheet-pdf.com/
1 page  
ASAHI KASEI
[AK8856VN]
22 DATA1
23 DATA0
24 NC
25 NC
26 TEST1
27 DTCLK
28 SDA
29 PVDD
30 SCL
31 OE
32 RSTN
33 DVDD
34 PDN
35 TEST0
36 NC
37 NC
38 XTO
39 DVSS
40 XTI
MS0522-E-00
Data output
P I/O - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1)
- this pin is used as an I/O pin in test mode
P
O
Data output pin ( LSB )
- output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1)
No connection – leave floating
- Reserved for AKM testing
No connection – leave floating
- Reserved for AKM testing
P
I
Test mode 1
- connect this pin to DVSS (internally pulled-down)
Data clock for output interface
P
I/O
- output state is separately controlled by combinations of RSTN/PDN/OE pin
settings (note 1)
- this pin is used as an I/O pin in test mode
I2C data
P
I/O
- this pin is pulled-up to PVDD
- Hi-Z input is allowed when PDN is low
- SDA input is not accepted during reset operation
Power supply for interface
P P - interface power supply for DTCLK, OE, PDN, RSTN, DATA[7:0], HD/HV,
VD/VAF/FIELD, NSIG, DVALID, SDA, SCL.
I2C clock input
P
I
- an input level below PVDD should be input
- Hi-Z input is allowed when PDN is low
- SCL input is not accepted during reset operation
Output enable
P
I
- L : digital output pins are at high-Z
- H : data is available for output
- Hi-Z input on OE pin is prohibited
Reset signal input
P
I
- Hi-Z input to this pin is prohibited
- L: reset
- H: normal operation
D P Digital power supply
Power-down control
P
I
- Hi-Z input to this pin is prohibited
- L: power-down
- H: normal operation
P
I
Test mode 0
- connect this pin to DVSS (internally pulled-down)
No connection – leave floating
- Reserved for AKM testing
No connection – leave floating
- Reserved for AKM testing
Quartz crystal oscillator connection (tie to digital ground via a 22pF capacitor)
- 27.00 MHz crystal oscillator should be used.
D O - this pin outputs DVSS level when PDN = L.
- when a crystal oscillator is not used, this pin can either be left open (NC) or
connected to DVSS
D G Digital ground pins
D
I
Quartz crystal oscillator connection (tie to digital ground via a 22pF capacitor)
- 27.00 MHz crystal oscillator should be used
5 2006/Dec
Free Datasheet http://www.datasheet-pdf.com/
5 Page 
ASAHI KASEI
[AK8856VN]
(DVDD = PVDD = 1.65V, Ta at -30 ~ +85°C)
Load condition: CL = 15pF
AC Timing
(1) CLK
Clock conditions (CLKMOD = 1: external clock mode)
tC L K L
fC L K
tC L K H
0 .8 D V D D
1/2 Level of 0.8PVD D and 0.2PVD D
0 .2 D V D D
Parameter
CLK
CLK duty ratio
Frequency stability
Symbol
fCLK
pCLKD
Min Typ
27.00
40
Max
60
±100
Unit
MHz
%
ppm
(2) Clock specification (DTCLK output)
Parameter Symbol
DTCLK
fDTCLK
Min.
Typ.
12.2727
13.5
24.5454
27
Max
Unit
MHz
Operating mode
QVGA / Rotate QVGA / Rotated CIF
CIF(PAL), QCIF
VGA
CIF(NTSC)/601
MS0522-E-00
11
2006/Dec
Free Datasheet http://www.datasheet-pdf.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK8856VN.PDF ] | |
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