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PDF AK8856 Data sheet ( Hoja de datos )

Número de pieza AK8856
Descripción NTSC/PAL Digital Video Decoder
Fabricantes AKM 
Logotipo AKM Logotipo



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ASAHI KASEI
[ AK8856 ]
AK8856
NTSC/PAL Digital Video Decoder
General Description
The AK8856 decodes NTSC or PAL composite video signals into digital video data. The outputs are ITU-R BT.
601 level compatible Y, Cb and Cr signals. The decoded result is scaled to 601, VGA (interlaced output), CIF,
QVGA, QCIF, rotated QVGA , or rotated CIF(progressive). Information including closed caption, VBID, and WSS
are encoded in the video signal can be read out externally. The AK8856 is controlled by through an I2C interface.
Features
NTSC-M, NTSC-4.43 / PAL- B, D, G, H, I, N, Nc, M, 60 composite signal decoding process
10 Bit ADC (sampling at 24.5454MHz or 27MHz)
Integrated PGA (0dB ~ 12dB)
Automatic color control (ACC) function
Adaptive automatic gain control (AGC) function
1D or 2D YC separation
Phase compensation for PAL
Output interface
- ITU-R BT.656 output format (4:2:2 8-bit parallel output with EAV / SAV)
- Camera interface
- Interface with HD / VD / DVALID signals
Closed caption decoding function (read by register setting)
VBID (CGMS-A) decoding function (CRCC decode) (read by register setting)
WSS decoding function (read by register setting)
Macrovision signal detect function
Power-down function
2-channel analog input selector
I2C control compatible
Core voltage (AVDD, DVDD) 1.65 - 1.8V
I/O voltage (PVDD) 1.65 - 3.3V (AK8856VG) / 1.65 - 3.6V (AK8856VN)
Package: 41 FBGA 4.0mm x 4.0mm / 48 QFN 7.2mm x 7.2mm
* The output that meets the ITU-R BT.656 standard according to the fineness of the input signal might not be available.
Rev-01
1
2007/03
Free Datasheet http://www.datasheet-pdf.com/

1 page




AK8856 pdf
ASAHI KASEI
AK8856VN
[ AK8856 ]
NC
NC
AVDD
AVSS
AIN2
DVSS
DVDD
NSIG
MACDET
DVALID
NC
NC
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
48 QFN
6 31
(TOP VIEW)
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
NC
TEST0
PDN
DVDD
RSTN
OE
SCL
PVDD
SDA
DTCLK
TEST1
NC
Rev-01
5
2007/03
Free Datasheet http://www.datasheet-pdf.com/

5 Page





AK8856 arduino
ASAHI KASEI
[ AK8856 ]
- input from 27.00 MHz crystal oscillator is connected to this pin
Clock mode set: connect to either DVDD (high) or DVSS (low)
41 CLKMOD
D
I - Low setting: crystal oscillator is used
- High setting: external clock source is used
Internal negative reference voltage for ADC
- connect this pin to analog ground through a 0.1uF or larger capacitor
42 VRN
A I/O - this pin may go to high-Z in power-down mode (no high-Z test is performed in
production test)
- do not use this as a reference voltage source for external circuitry
Internal positive reference voltage for ADC
- connect this pin to analog ground through a 0.1uF or larger capacitor
43 VRP
A I/O - there is a case when this pin becomes Hi-Z output at power-down ( no Hi-Z test is
performed in mass-production test )
- do not use this pin as a reference voltage source for external circuit.
Reference current setting
44 IREF
A
I/O
- connect this pin to analog ground through a 6.8kΩ resistor (1% accuracy)
- this pin goes to high-Z in power-down mode (no high-Z test is performed in
production test)
Internal common voltage for AD converter
- connect this pin to analog ground via a 0.1 uF or larger capacitor.
45 VCOM
A I/O - there is case when this pin becomes Hi-Z output at power-down (no Hi-Z test is
performed in mass-production test ).
- do not use this pin as a reference voltage source for external circuit.
46 LPF
A
I/O
I/O for analog test
- connect this pin to AVSS for normal operation
47 AIN1
A I Analog input pin (1) ; if not used, leave floating
48 NC
No connection – leave floating
- Reserved for AKM testing
A/D/P A: AVDD, D: DVDD, P: PVDD
I/O I: Input pin, O: Output pin, I/O Input/Output pin
Note 1 ) Output pin conditions are determined by setting PDN and OE pins
OE
PDN
RSTN
Output1*
Output2*
L x x Hi-Z output L output
H
L
x
L output
L output
H
H
L
L output
L output
H Dataout(*1) Dataout(*1)
Output1*: DATA[7:0], HD/HV, VD/VAF/FIELD, DVALID, DTCLK
Output2*: NSIG, MACDET
Output pin conditions immediately following power-on are indeterminate, except at OE = “L“
(*1 ) With no analog input signal, black level data (Y = 0x10, Cb/Cr = 0x80) is output in decoder mode operation
Rev-01
11
2007/03
Free Datasheet http://www.datasheet-pdf.com/

11 Page







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