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PDF BU9409FV Data sheet ( Hoja de datos )
| Número de pieza | BU9409FV | |
| Descripción | 32bit Audio DSP | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de BU9409FV (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Digital Sound Processors for FPD TVs
32bit Audio DSP
BU9409FV
No.12083EAT03
●General Description
It is a digital audio sound processor used for thin TV. Digital signal processor is Rohm original DSP only for TV
sound signal processing, and it’s cost performance is excellent. Digital inputs are two lines. Output is digital output
corresponding to 2.1ch or play of sub-voice L/R signal.
●Features
■DSP Part
Data width:
32bit (Data RAM)
Quickest machine cycle:40.7ns (512fs,fs=48kHz)
Multiplier:
32 x 24 → 56bit
Adder:
32 + 32 → 32bit
Data RAM:
256 x 32bit
Coefficient RAM:
128 x 24bit
Sampling frequency: fs=48kHz
Master clock:
512fs
（24.576MHz,fs=48kHz）
■Input output I/F
2 stereo digital signal input port : 16/20/24bit (I2S,left-align,right-align)
2 stereo digital signal output port : 16/20/24bit (I2S,left-align,right-align), S/PDIF output
■Sound signal processing function for TV
Prescaler, DC cut HPF, channel mixer, P2Volume(Perfect Pure Volume),BASS,MIDDLE,
TREBLE, pseudo stereo, surround, P2Bass, P2Treble, 7 band parametric equalizer,
master volume, L/R balance, postscaler, output clipper, subwoofer output processing
（P2Volume，P2Bass，P2Treble are Rohm original sound effect functions.）
●Applications
Flat Panel TVs (LCD, Plasma)
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
1/54
2012.03 - Rev.A
Free Datasheet http://www.datasheet-pdf.com/
1 page  
BU9409FV
Technical Note
●Pin Description(s)
No. Name
1 N.C
Description of terminals
(*2)
Type No.
Name
- 21 ADDR
Description of terminals
Type
I2C Slave address selection B
2 LRCKI
I2S Audio LR signal input
D
3 SDATA1
I2S Audio data input 1
D
4 SDATA2
I2S Audio data input 2
D
5 RESETX
Reset status with “L”
B
6 MUTEX_SP DAC mute signal input(*1)
B
7 MUTEX_DAC SP mute signal input(*1)
B
8 SCLI
I2C Forwarding clock input
F
9 SDAI
I2C Data input output
E
10 VSS1
Digital I/O GND
-
11 DVDDCORE Connect to REG15 terminal
-
12 REG15
Built-in regulator voltage output G
13 LDOPOFF Built-in regulator POFF signal G
22 SPDIFO
23 N.C
24 N.C
25 N.C
26 N.C
27 N.C
28 SDAO
29 SCLO
30 MUTEX_DACO
31 MUTEX_SPO
32 RESETXO
33 SDATAO2
terminal
S/PDIF Signal output
2 line serial data output（*1）
2 line serial clock output（*1）
DAC mute signal output(*1)
SP mute signal output(*1)
Reset signal output(*1)
I2S Audio data output 2
C
-
-
-
-
-
C
C
C
C
C
C
14 ANATEST
15 VDD
16 N.C
17 N.C
18 PLLFIL
input
Analog test monitor terminal
Digital I/O power supply
Filter connection terminal for
G
-
-
-
G
34 SDATAO1
35 LRCKO
36 BCKO
37 SYSCLKO
38 VSS3
I2S Audio data output 1
I2S Audio LR signal output 1
I2S Audio clock output 1
System clock output（*1）
Digital I/O GND
C
C
C
C
-
PLL
19 VSS2
Digital I/O GND
- 39 MCLK
Master clock input
20 MODE
Test mode selection input
A 40 BCKI
I2S Audio clock input
N.C.：Non Connection
(*1)：signal terminal is used with D class amplifier IC (BD5446EFV etc.) for input I2S made by Rohm.
(*2) ：It connects with the lead frame of a package. Please use by OPEN or GND connection.
H
D
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
5/54
2012.03 - Rev.A
Free Datasheet http://www.datasheet-pdf.com/
5 Page 
BU9409FV
Technical Note
2-4. Output data selection(SEL2) to P-S conversion2 (SDATAO2 Terminal)
Default = 0
Select Address
&h04 [ 5：4 ]
Value
0
1
2
3
Operating Description
Sub data output after DSP is processed.
Main data output after DSP is processed.
Sub data output before DSP is processed.
Main data output before DSP is processed.
2-5. SPDIFO Terminal output data selection（SEL2）
Default = 0
Select Address
&h05 [ 1：0 ]
Value
0
1
2
3
Operating Description
Main data output after DSP is processed.
Sub data output after DSP is processed.
Main data output before DSP is processed.
Sub data output before DSP is processed.
2-6. System clock selection（SEL3）
Select the DSP clock supplied to S-P conversion1、S-P conversion2、DSP、P-S conversion1、P-S conversion2、S/PDIF
output part.
Default = 0
Select Address
&h08 [ 5：4 ]
Value
0
Operating Description
Chose the input from a MCLK terminal as a clock.
1 Chose the PLL output as a clock.
2
Chose the input from a SDATA2terminal as a clock. (used for IC test).
3
After power on or reset released, system block selection uses clock(even if not 512fs is ok) input from terminal MCLK to
receive I2C command and initialize BU9409. Then set the dividing frequency ratio of PLL block (mclk_div, pll_div) that is
suitable for the clock frequency from terminal MCLK , when PLL_512fs clock from PLL is steady, set &h08 = 10h.
2-7. Dividing frequency ratio setting of PLL block which corresponding to input clock from terminal MCLK
Sampling rate of input clock
Setting of mclk_div
Setting of pll_div
PLL initialization
&hF3
&hF5
&hF6
512fs（24.576MHz、fs=48kHz）
256fs（12.288MHz、fs=48kHz）
128fs（6.144MHz、fs=48kHz）
10h
08h
04h
01h
01h
01h
23h
23h
23h
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
11/54
2012.03 - Rev.A
Free Datasheet http://www.datasheet-pdf.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
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