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PDF CY7C1061DV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1061DV33 | |
| Descripción | 16-Mbit (1 M X 16) Static RAM | |
| Fabricantes | Cypress | |
| Logotipo |  |
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CY7C1061DV33
16-Mbit (1 M × 16) Static RAM
16-Mbit (1 M × 16) Static RAM
Features
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 175 mA at 100 MHz
■ Low CMOS standby power
❐ ISB2 = 25 mA
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE1 and CE2 features
■ Available in Pb-free 54-pin TSOP II and 48-ball VFBGA
packages
■ Offered in single CE and dual CE options
Functional Description
The CY7C1061DV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A19). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 12
for a complete description of Read and Write modes.
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE1 HIGH/CE2
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH, and WE LOW).
The CY7C1061DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and 48-ball
VFBGA packages.
For a complete list of related documentation, click here.
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
AA34
AA56
1M x 16
ARRAY
AAA789
I/O0 – I/O7
I/O8 – I/O15
COLUMN
DECODER
BHE
WE
OE
BLE
CE2
CE1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05476 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 27, 2015
1 page  
CY7C1061DV33
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature
with Power Applied .................................. –55 C to +125 C
Supply Voltage
on VCC relative to GND [5] ...........................–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State [5] ................................ –0.5 V to VCC + 0.5 V
DC Input Voltage [5] ............................ –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................. >2001 V
Latch Up Current .................................................... >200 mA
Operating Range
Range
Industrial
Ambient Temperature
–40 C to +85 C
VCC
3.3 V 0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
VOH Output HIGH voltage
VOL Output LOW voltage
VIH Input HIGH voltage
VIL Input LOW voltage [5]
IIX Input leakage current
IOZ Output leakage current
ICC VCC operating supply current
ISB1 Automatic CE power down
current – TTL inputs
ISB2 Automatic CE power down
current – CMOS inputs
Test Conditions
VCC = Min, IOH = –4.0 mA
VCC = Min, IOL = 8.0 mA
–
–
GND < VI < VCC
GND < VOUT < VCC, Output disabled
VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA,
CMOS levels
Max VCC, CE1 > VIH, CE2 < VIL,
VIN > VIH or VIN < VIL, f = fMAX
Max VCC, CE1 > VCC – 0.3 V, CE2 < 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
Min
2.4
–
2.0
–0.3
–1
–1
–
-10
Max
–
0.4
VCC + 0.3
0.8
+1
+1
175
Unit
V
V
V
V
A
A
mA
– 30 mA
– 25 mA
Note
5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
Document Number: 38-05476 Rev. *J
Page 5 of 19
5 Page 
CY7C1061DV33
Switching Waveforms (continued)
Figure 11. Write Cycle No. 3 (BLE or BHE Controlled) [25]
Address
tWC
BHE, BLE
WE
CE
Data I/O
tSA tBW
tAW
tPWE
tSCE
tHA
tSD tHD
Note
25.
For
CE
all packages
is HIGH. For
except -BV1XI, CE is
-BV1XI package, CE
the logical combination
refers to CE.
of
CE1
and
CE2.
When
CE1
is
LOW
and
CE2
is
HIGH,
CE
is
LOW;
when
CE1
is
HIGH
or
CE2
is
LOW,
Document Number: 38-05476 Rev. *J
Page 11 of 19
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