PDF HY5PS121621CFP Data sheet ( Hoja de datos )

Número de pieza	HY5PS121621CFP
Descripción	DDR2 SDRAM
Fabricantes	Hynix
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No Preview Available ! HY5PS121621CFP 512Mb(32Mx16) DDR2 SDRAM HY5PS121621CFP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.3/ Feb. 2007 1 Free Datasheet http://www.datasheet4u.net/ 1 page 1HY5PS121621CFP 1. Description 1.1 Device Features & Ordering Information 1.1.1 Key Features • VDD/VDDQ= 2.0V +/- 0.1V(500 / 450 MHz) • VDD/VDDQ= 1.8V +/- 0.1V(400 / 350 / 300 MHz) • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data Strobe (DQS, DQS) • Data outputs on DQS, DQS edges when read (edged DQ) • Data inputs on DQS centers when write(centered DQ) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM mask write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency from 3 to 7 supported • Programmable additive latency 0, 1, 2, 3, 4,5 and 6 supported • Programmable burst length 4/8 with both nibble sequential and interleave mode • Internal four bank operations with single pulsed RAS • Auto refresh and self refresh supported • tRAS lockout supported • 8K refresh cycles /64ms • JEDEC standard 84ball FBGA(x16) • Full strength driver option controlled by EMRS • On Die Termination supported • Off Chip Driver Impedance Adjustment supported • Self-Refresh High Temperature Entry • High Temperature Self Refresh rate supported Ordering Information Part No. HY5PS121621CFP-2 HY5PS121621CFP-22 HY5PS121621CFP-25 HY5PS121621CFP-28 HY5PS121621CFP-33 Power Supply VDD/ VDDQ=2.0V VDD/ VDDQ=1.8V Clock Frequency 500Mhz 450Mhz 400Mhz 350Mhz 300MHz *** HY5PS121621CFP-2 do not guarantee -25/-28/-33 speed bin. Max Data Rate Interface Package 1000Mbps/pin 900Mbps/pin 800Mbps/pin 700Mbps/pin 600Mbps/pin SSTL_18 84Ball FBGA Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials. We'll add "P" character after "F" for Lead free product. For example, the part number of 300MHz Lead free product is HY5PS121621CFP-33.. Rev. 1.3/ Feb. 2007 5 Free Datasheet http://www.datasheet4u.net/ 5 Page 1HY5PS121621CFP 13. If OCD calibration is not used, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of EMRS. 14. The DDR2 SDRAM is now ready for normal operation. 1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. 2) Sequence 5 and 6 may be performed between 8 and 9. Initialization Sequence after Power Up tCHtCL CK /CK tIS CKE ODT Command NOP PRE ALL EMRS MRS PRE ALL REF 400ns tRP tMRD tMRD tRP DLL ENABLE DLL RESET REF tRFC tRFC min. 200 Cycle MRS EMRS EMRS ANY CMD tMRD Follow OCD Flowchart tOIT OCD Default OCD CAL. MODE EXIT 2.3.2 Programming the Mode and Extended Mode Registers For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive CAS latency, ODT(On Die Termination), single-ended strobe, and OCD(off chip driver imped- ance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register(MR) or Extended Mode Registers(EMR(#)) can be altered by re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents. Rev. 1.3/ Feb. 2007 11 Free Datasheet http://www.datasheet4u.net/ 11 Page

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