PDF NT5SV8M16FT Data sheet ( Hoja de datos )

Número de pieza	NT5SV8M16FT
Descripción	128Mb Synchronous DRAM
Fabricantes	NANYA
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No Preview Available ! NT5SV8M16FS / NT5SV8M16FT 128Mb Synchronous DRAM Features • High Performance: Maximum Operating Speed CAS Latency PC166 PC133 (6K/6KI) (75B/75BI) 2 7.5 10 ns 3 6 7.5 ns • Single Pulsed RAS Interface • Fully Synchronous to Positive Clock Edge • Four Banks controlled by BA0/BA1 (Bank Select) • Programmable CAS Latency: 2, 3 • Programmable Burst Length: 1, 2, 4, 8 or full page • Programmable Wrap: Sequential or Interleave • Multiple Burst Read with Single Write Option • Automatic and Controlled Precharge Command • Dual Data Mask for byte control (x16) • Auto Refresh (CBR) and Self Refresh • Suspend Mode and Power Down Mode • Standard Power operation • Random Column Address every CK (1-N Rule) • Single Power Supply, either 3.3V • LVTTL compatible • Packages: TSOP-Type II • Lead-free & Halogen-free product available Description The NT5SV8M16FS, and NT5SV8M16FT are four-bank Syn- chronous DRAMs organized as 2Mbit x 16 I/O x 4 Bank. These synchronous devices achieve high-speed data trans- fer rates of up to 166MHz by employing a pipeline chip archi- tecture that synchronizes the output data to a system clock. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/out- put (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are exam- ined at the positive edge of each externally applied clock (CK). Internal chip operating modes are defined by combina- tions of these signals and a command decoder initiates the necessary timings for each operation. A fifteen bit address bus accepts address data in the conventional RAS/CAS mul- tiplexing style. Twelve addresses (A0-A11) and two bank select addresses (BA0, BA1) are strobed with RAS. Nine col- umn addresses (A0-A8) plus bank select addresses and A10 are strobed with CAS. Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A11, BA0, BA1 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gap- less data rate of up to 166MHz is possible depending on burst length, CAS latency, and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are sup- ported. REV 1.3 9/2008 1 © NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. Free Datasheet http://www.datasheet4u.net/ 1 page NT5SV8M16FS / NT5SV8M16FT 128Mb Synchronous DRAM Block Diagram CKE CKE Buffer CK CK Buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 BA1 BA0 A10 CS RAS CAS WE Column Decoder Cell Array Memory Bank 0 Sense Amplifiers Column Decoder Cell Array Memory Bank 2 Sense Amplifiers Column Decoder Cell Array Memory Bank 1 Sense Amplifiers DQ0 DQX DQM Column Decoder Cell Array Memory Bank 3 Sense Amplifiers Cell Array, per bank, for 4Mb x 16 DQ: 4096 Row x 512 Col x 16 DQ (DQ0-DQ15). REV 1.3 9/2008 5 © NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. Free Datasheet http://www.datasheet4u.net/ 5 Page NT5SV8M16FS / NT5SV8M16FT 128Mb Synchronous DRAM Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS latency that is set in the Mode Register. Burst Read Operation (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND READ A NOP NOP NOP NOP NOP NOP NOP NOP CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Read Interrupted by a Read A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remain- ing addresses are overridden by the new address with the burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command appears. Read Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND READ A READ B NOP NOP NOP NOP NOP NOP NOP CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 REV 1.3 9/2008 11 © NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. Free Datasheet http://www.datasheet4u.net/ 11 Page

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