|
|
PDF APL5338 Data sheet ( Hoja de datos )
| Número de pieza | APL5338 | |
| Descripción | 2A Bus Termination Regulator | |
| Fabricantes | Anpec Electronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de APL5338 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
|
No Preview Available !
APL5338
2A Bus Termination Regulator
Features
General Description
• Sourcing and Sinking Current up to 2A
The APL5338 linear regulator is designed to provide a
• Wide Input Voltage Range: 1.2V to 3.6V
regulated voltage with bi-directional output current for
•
DDR-SDRAM termination. The APL5338 integrates two
VTT and VTTREF Voltage Tracks at Half the VREF
power transistors to source or sink current up to 2A. It
Voltage
also incorporates current-limit and thermal shutdown into
• VTT and VTTREF Voltage with ±10mV Accuracy a single chip.
• Excellent Load Transient Response
The output voltage of APL5338 tracks the voltage at VREF
• Stable with 10µF Ceramic Output Capacitor
pin. An internal resistor divider is used to provide a half
• Current-Limit Protection
• Thermal Shutdown Protection
• Power-On-Reset Function on VCNTL
• S3, S5 Input Signals for ACPI States
voltage of VREF for VTTREF and VTT Voltage. The VTT
output voltage is only requiring 10µF of ceramic output
capacitance for stability and fast transient response. The
S3 and S5 pins provide the sleep state for VTT (S3 state)
and suspend state (S4/S5 state) for device when S5 and
• Small MSOP-10P and TDFN3x3-10 Packages
S3 are both pulled low the device provides the soft-off for
• Lead Free and Green Devices Available
(RoHS Compliant)
VTT and VTTREF. The MSOP-10P and TDFN3x3-10 pack-
age with a copper pad is available which provides excel-
lent thermal impedance.
Applications
• DDR 2/3 Memory Termination
Simplified Application Circuit
CIN
10µF
COUT
10µF
APL5338
1 VREF
10
VCNTL
2 VIN
S5 9
3
VTT
GND 8
4
PGND
S3 7
5 VTTSNS VTTREF 6
C1
0.1µF
Pin Configuration
VREF 1
VIN 2
VTT 3
PGND 4
VTTSEN 5
10 VCNTL
9 S5
8 GND
7 S3
6 VTTREF
MSOP-10P (Top View)
VREF 1
VIN 2
VTT 3
PGND 4
VTTSEN 5
GND
10 VCNTL
9 S5
8 GND
7 S3
6 VTTREF
TDFN3X3-10
(Top View)
= Exposed Pad
(connected to ground plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.5 - Aug., 2013
1
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
1 page  
APL5338
Typical Operating Characteristics
VCNTL Supply Current vs. Temperature
0.60
VCNTL=5V
VS3=VS5=5V
0.55
0.50
0.45
0.40
-40 -20 0 20 40 60 80 100 120 140
Junction Temperature (oC)
VIN Supply Current vs. Temperature
1.6
VCNTL=5V
1.4 VS3=VS5=5V
1.2
1.0
0.8
0.6
0.4
0.2
-40 -20 0 20 40 60 80 100 120 140
Junction Temperature (oC)
VTTREF Output Voltage vs. Temperature
0.910
0.908
0.906
0.904
VCNTL=5V
VIN=VREF=1.8V
IVTTREF=0mA
0.902
0.900
0.898
0.896
0.894
0.892
0.890
-40 -20 0 20 40 60 80 100 120 140
Junction Temperature (oC)
Copyright © ANPEC Electronics Corp.
Rev. A.5 - Aug., 2013
5
VCNTL Shutdown Current vs. Temperature
1.0
0.9
VCNTL=5V
VS3=VS5=0V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-40 -20 0 20 40 60 80 100 120 140
Junction Temperature (oC)
VIN Shutdown Current vs. Temperature
1.0
VCNTL=5V
0.9 VS3=VS5=0V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-40 -20 0 20 40 60 80 100 120 140
Junction Temperature (oC)
VTT Output Voltage vs. Temperature
0.910
0.908
0.906
VCNTL=5V
VIN=VREF=1.8V
0.904
0.902
IVTT=-10mA
0.900
0.898
IVTT=10mA
0.896
0.894
0.892
0.890
-40 -20 0 20 40 60 80 100 120 140
Junction Temperature (oC)
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
5 Page 
APL5338
Application Information
Input Capacitor
The APL5338 requires proper input capacitors to supply
surge current during stepping load transients to prevent
the input rail from dropping. Because the parasitic induc-
tor from the voltage sources or other bulk capacitors to
the VIN limits the slew rate of the surge current, it is nec-
essary to place the input capacitors near VIN as close as
possible. Input capacitors should be greater than 10µF. A
capacitor of 0.1µF (MLCC) or above is recommended for
VCNTL pin noise decoupling.
Output Capacitor
The APL5338 needs a proper output capacitor to main-
tain circuit stability and improve transient response over
temperature and current. In order to insure the circuit
stability, a 10µF MLCC (minimum) as an output capacitor
must be placed near the VTT. W ith X5R and X7R
dielectrics.
Thermal Consideration
The APL5338 maximum power dissipation depends on
the differences of the thermal resistance and tempera-
ture between junction and ambient air. The power dissi-
pation P across the device is:
D
PD = (TJ - TA) / θJA
where (TJ-TA) is the temperature difference between the
junction and ambient air. θJA is the thermal resistance
between junction and ambient air. Assuming the TA=25°C
and maximum TJ=150°C (typical thermal limit threshold),
the maximum power dissipation is calculated as:
PD(max)=(150-25)/60
= 2.08(W)
For normal operation, do not exceed the maximum oper-
ating junction temperature of TJ = 125°C. The calculated
power dissipation should be less than:
P =(125-25)/60
D
= 1.66(W)
The exposed pad provides an electrical connection to
ground and channels heat away. Connect the exposed
pad to ground by using a large ground plane.
Layout Consideration
Figure 1 illustrates the layout. Below is a checklist for
your layout:
1. Please place the input capacitors close to the VIN.
2. Output capacitors for VTT must be close to the pin with
short and wide track.
3. VTTSNS should be connected to the output capacitors
of VTT separated from large current path to avoid ef-
fect of ESR and ESL. The ESR and ESL of ground track
between VTT and GND should be minimized.
4. VREF should be connected to VIN by a separate track.
VREF is the reference voltage of VTTREF, so avoid any
noise to get into the VREF.
5. PGND is the ground of VIN and VTT. GND is the signal
ground of VREF, VTTREF S3 and S5. GND and PGND
should be isolated with a single point connection be-
tween them.
6. Soldering the exposed pad to ground is good for
heatsinking. Numerous vias 0.33 mm in diameter con-
nected from the thermal land to the internal/solder-
side ground plane(s) should be used to enhance
dissipation.
Large ground plane is good for heatsinking. Optimum
performance can only be achieved when the device is
mounted on a PC board according to the board layout
diagrams which are shown as Figure 2.
VIN
CIN
VTT
COUT
APL5338
1
VREF
10
VCNTL
2 VIN
9
S5
3
VTT
GND 8
4
PGND
S3 7
56
VTTSNS VTTREF
VCNTL
5V
C2
C1
Figure 1
Copyright © ANPEC Electronics Corp.
Rev. A.5 - Aug., 2013
11
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet APL5338.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| APL5330 | Dual Input 2A Low Dropout Regulator | Anpec Electronics |
| APL5331 | 3A Bus Termination Regulator | Anpec Electronics |
| APL5332 | CMOS LDO | Anpec Electronics |
| APL5333 | 3A Bus Termination Regulator | Anpec Electronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |