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PDF APL5333 Data sheet ( Hoja de datos )
| Número de pieza | APL5333 | |
| Descripción | 3A Bus Termination Regulator | |
| Fabricantes | Anpec Electronics | |
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APL5333
3A Bus Termination Regulator
Features
• Sourcing and Sinking Current up to 3A
• Wide Input Voltage Range: 1.2V to 3.6V
• VTT and VTTREF Voltage Tracks at Half the
VREF Voltage
• VTT and VTTREF Voltage with ±20mV Accuracy
• Excellent Load Transient Response
- Droop Compensation
- Fast Loop Response
• Stable with 20µF Ceramic Output Capacitors
• Current Limit Protection
• Thermal Shutdown Protection
• Power-On-Reset Function on VCNTL
• S3, S5 Input Signals for ACPI States
• Available in a Thermal Enhanced MSOP-10P
Package
• Lead Free Available (RoHS Compliant)
Applications
• DDR 1/2/3 Memory Termination
• SSTL-2, STL-18 and HSTL Termination
General Description
The APL5333 linear regulator is designed to provide a
regulated voltage with bi-directional output current for
DDR-SDRAM termination. The APL5333 integrates two
power transistors to source or sink current up to 3A. It
also incorporate current-limit, thermal shutdown into a
single chip.
The output voltage of APL5333 tracks the voltage at VREF
pin. An internal resistor divider is used to provide a half
voltage of VREF for VTTREF and VTT Voltage. The VTT
output voltage is only requiring 20µF of ceramic output
capacitance for stability and fast transient response. The
S3 and S5 pins provide the sleep state for VTT (S3 state)
and suspend state (S4/S5 state) for device, when S5 and
S3 are both pulled low the device provides the soft-off for
VTT and VTTREF. The MSOP-10P package with a copper
pad is available which provides excellent thermal
impedance.
Simplified Application Circuit
VIN
VCNTL
APL5333
1 VREF
10
VCNTL
5V
2 VIN
S5 9
VTT
3 VTT
GND 8
4
PGND
S3 7
5 VTTSNS
6
VTTREF
Ordering and Marking Information
APL5333
Lead Free Code
Handling Code
Temperature Range
Package Code
Package Code
XA : MSOP-10P
Temperature Range
I : - 40 to 85 oC
Handling Code
TR : Tape & Reel
Lead Free Code
L : Lead Free Device
APL5333 XA :
L5333
XXX
XX
X - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte in plate termination finish; which are fully compliant
with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-free requirements of
IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.1 - Feb., 2008
1
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
1 page  
APL5333
Typical Operating Characteristics
(Refer to the section “Typical Application Circuits”, VCNTL=5V, VIN=VREF=1.8V, VTT=0.9V, TA=25oC)
Frequency Response
40
Frequency Response
200
20 150
0
-20 VTT=1.25V, IVTT=+2.5A
VTT=0.75V, IVTT=+2.5A
-40
-60
100
50 VTT=1.25V, IVTT=+2.5A
0
-50 VTT=0.75V, IVTT=+2.5A
-80
1000
10000
100000
Frequency (Hz)
1000000
VCNTL PSRR
0
-10 VTT=1.25V, IVTT=+1.5A
VTT=0.75V, IVTT=+1.5A
-20 VTT=0.9V, IVTT=+1.5A
-30
-40
-50
-60
1000
10000
Frequency (Hz)
100000
Dropout Voltage vs. VTT Output Current
1000
900
VTT=0.75V
800 TJ=125oC
700 TJ=75oC
600 TJ=25oC
500
400
300
200
100
0
0
TJ=-50oC
TJ=-25oC
12
VTT Output Current, IVTT(A)
3
Copyright © ANPEC Electronics Corp.
Rev. A.1 - Feb., 2008
5
-100
1000
10000
100000
Frequency (Hz)
1000000
VCNTL Supply Current vs. VCNTL Voltage
800
700 S3=S5=high
600
500
400
300 VVCNTL=5V
200
100
0
0123456
VCNTL Voltage, VCNTL (V)
Dropout Voltage vs. VTT Output Current
1000
900
VTT=0.9V
800 TJ=125oC
700 TJ=75oC
600 TJ=25oC
500
400
300
200
100
0
0
TJ=-50oC
TJ=-25oC
12
VTT Output Current, IVTT(A)
3
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
5 Page 
APL5333
Application Information
Input Capacitor
The APL5333 requires proper input capacitors to supply
surge current during stepping load transients to prevent
the input rail from dropping. Because the parasitic induc-
tor from the voltage sources or other bulk capacitors to
the VIN limits the slew rate of the surge current, it is nec-
essary to place the input capacitors near VIN as close as
possible. Input capacitors should be greater than 4.7µF. A
capacitor of 0.47µF (MLCC) or above is recommended
for VCNTL pin noise decoupling.
Output Capacitor
The APL5333 needs a proper output capacitor to main-
tain circuit stability and improve transient response over
temperature and current. In order to insure the circuit
stability, a 4.7µF MLCC (minimum) as an output capaci-
tor must be placed near the VTT. With X5R and X7R
dielectrics, 20µF is sufficient at all operating temperatures.
Attaching two 10µF ceramic capacitors in parallel, the ef-
fects from ESR and ESL can be minimized.
Thermal Consideration
The APL5333 maximum power dissipation depends on
the differences of the thermal resistance and tempera-
ture between junction and ambient air. The power dissi-
pation PD across the device is:
PD = (TJ - TA) / JA
where (T -T ) is the temperature difference between the
JA
junction and ambient air. is the thermal resistance
JA
between junction and ambient air. Assuming the TA=25°C
and maximum TJ=150°C (typical thermal limit threshold),
the maximum power dissipation is calculated as:
P =(150-25)/60
D(max)
= 2.08(W)
For normal operation, do not exceed the maximum oper-
ating
junction
temperature
of
T
J
=
125°C.
The
calculated
power dissipation should be less than:
PD =(125-25)/60
= 1.66(W)
The exposed pad provides an electrical connection to
ground and channels heat away. Connect the exposed
pad to ground by using a large ground plane.
Layout Consideration
Figure 1 illustrates the layout. Below is a checklist for
your layout:
1. Please place the input capacitors close to the VIN.
2. Output capacitors for VTT must be close to the pin with
short and wide track.
3. VTTSNS should be connected to the output capacitors
of VTT separated from large current path to avoid ef-
fect of ESR and ESL. The ESR and ESL of ground track
between VTT and GND should be minimized.
4. VREF should be connected to VIN by a separate track.
VREF is the reference voltage of VTTREF, so avoid any
noise to get into the VREF.
5. PGND is the ground of VIN and VTT. GND is the signal
ground of VREF, VTTREF S3 and S5. GND and PGND
should be isolated with a single point connection be-
tween them.
6. Soldering the exposed pad to ground is good for
heatsinking. Numerous vias 0.33 mm in diameter con-
nected from the thermal land to the internal/solder-
side ground plane(s) should be used to enhance
dissipation.
Large ground plane is good for heatsinking. Optimum
performance can only be achieved when the device is
mounted on a PC board according to the board layout
diagrams which are shown as Figure 2.
VIN
CIN
VTT
COUT
APL5333
1
VREF
10
VCNTL
2 VIN
S5 9
3
VTT
GND 8
4
PGND
S3 7
5 VTTSNS
6
VTTREF
VCNTL
5V
C2
C1
Figure 1
Copyright © ANPEC Electronics Corp.
Rev. A.1 - Feb., 2008
11
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet APL5333.PDF ] | |
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