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PDF CS61304A Data sheet ( Hoja de datos )
| Número de pieza | CS61304A | |
| Descripción | T1/E1 Line Interface | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CCSS6130044AA
TT11//EE11 Line Interface
Features
General Description
• Provides Analog Transmission Line
Interface for T1 and E1 Applications
• Provides Line Driver, Jitter Attenuator
and Clock Recovery Functions
• Fully Compliant with AT&T 62411
Stratum 4, Type II Jitter Requirements
• Low Power Consumption
• B8ZS/HDB3/AMI Encoder/Decoder
• 50 mA Transmitter Short-Circuit
Current Limiting
The CS61304A combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
The CS61304A is a pin-compatible replacement for the
LXT304A.
The receiver uses a digital Delay-Locked-Loop which is
continuously calibrated from a crystal reference to pro-
vide excellent stability and jitter tolerance. The
CS61304A has a receiver jitter attenuator optimized for
T1 CPE applications subject to AT&T 62411 and E1
ISDN PRI applications. The transmitter features inter-
nal pulse shaping and a low impedance output stage
allowing the use of external resistors for transmitter im-
pedance matching.
Applications
• Primary Rate ISDN Network/Termination Equipment
• Channel Service Units
ORDERING INFORMATION
See page 31.
( ) = Pin Function in Host Mode
[ ] = Pin Function in Extended Hardware Mode
(CLKE) (INT) (SDI) (SDO)
MODE TAOS LEN0 LEN1 LEN2 TGND TV+
TCLK
TPOS
[TDATA]
2
3
TNEG 4
AMI,
[TCODE]
B8ZS,
8 HDB3,
RCLK
CODER
RPOS
[RDATA]
RNEG
[BPV]
7
6
R
E
M
O
T
E
L
O
O
P
B
A
C
K
26
JITTER
ATTENUATOR
L
O
C
A
L
L
O
O
P
B
A
C
K
9 10
1
5 28
CONTROL
23 24 25
14 15
LINE DRIVER 13
PULSE
SHAPER
16
TTIP
TRING
CLOCK &
DATA
RECOVERY
SIGNAL
QUALITY
MONITOR
LINE RECEIVER
DRIVER
MONITOR
27 12
21
22
19 RTIP
20
RRING
17 MTIP
[RCODE]
18 MRING
[PCS]
11 DPM
[AIS]
RLOOP XTALIN XTALOUT ACLKI
(CS)
LLOOP
(SCLK)
LOS RV+
RGND
Preliminary Product Information This document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
Pht.tpO:/./wBwowx.c1ir7ru8s4.7co, mAustin, Texas, 78760
(512) 445-7222 FAX:(512) 445-7581
Copyright © Cirrus Logic, Inc. 2005
(AlCl RopigyhrtigshRt e©seCrvryesdt)al Semiconductor Corporation 1996
(All Rights Reserved)
SMEAPY‘0956
DDS1S5165P6PF12
1
Free Datasheet http://www.datasheet4u.com/
1 page  
CS61304A
CS61304A
T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol Min
Typ
Crystal Frequency
(Note 25)
fc
- 6.176000
TCLK Frequency
ftclk - 1.544
TCLK Pulse Width
(Note 26) tpwh2
150
-
ACLKI Duty Cycle
tpwh3/tpw3
40
-
ACLKI Frequency
(Note 27) faclki
- 1.544
RCLK Duty Cycle
(Note 28) tpwh1/tpw1
45
50
Rise Time, All Digital Outputs
(Note 29)
tr
--
Fall Time, All Digital Outputs
(Note 29)
tf
--
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2 25
-
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2 25 -
RPOS/RNEG Valid Before RCLK Falling
(Note 30) tsu1
150 274
RDATA Valid Before RCLK Falling
(Note 31) tsu1
150 274
RPOS/RNEG Valid Before RCLK Rising
(Note 32) tsu1
150 274
RPOS/RNEG Valid After RCLK Falling
(Note 30)
th1
150 274
RDATA Valid After RCLK Falling
(Note 31)
th1
150 274
RPOS/RNEG Valid After RCLK Rising
(Note 32)
th1
150 274
Notes: 25. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.
26. The transmitted pulse width does not depend on the TCLK duty cycle.
27. ACLKI provided by an external source or TCLK.
28. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached.
29. At max load of 1.6 mA and 50 pF.
30. Host Mode (CLKE = 1).
31. Extended Hardware Mode.
32. Hardware Mode, or Host Mode (CLKE = 0).
Max
-
-
500
60
-
55
85
85
-
-
-
-
-
-
-
-
E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Crystal Frequency
(Note 25)
TCLK Frequency
TCLK Pulse Width
(Note 26)
ACLKI Duty Cycle
ACLKI Frequency
(Note 27)
RCLK Duty Cycle
(Note 28)
Rise Time, All Digital Outputs
(Note 29)
Fall Time, All Digital Outputs
(Note 29)
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
(Note 30)
RDATA Valid Before RCLK Falling
(Note 31)
RPOS/RNEG Valid Before RCLK Rising
(Note 32)
RPOS/RNEG Valid After RCLK Falling
(Note 30)
RDATA Valid After RCLK Falling
(Note 31)
RPOS/RNEG Valid After RCLK Rising
(Note 32)
Symbol
fc
ftclk
tpwh2
tpwh3/tpw3
faclki
tpwh1/tpw1
tr
tf
tsu2
th2
tsu1
tsu1
tsu1
th1
th1
th1
Min Typ Max
- 8.192000 -
- 2.048 -
150 - 340
40 - 60
- 2.048 -
45 50 55
- - 85
- - 85
25 -
-
25 -
-
100 194
-
100 194
-
100 194
-
100 194
-
100 194
-
100 194
-
DS156PFP1 2
Units
MHz
MHz
ns
%
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
MHz
MHz
ns
%
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
Free Datasheet http://www.datasheet4u.com/
5 Page 
CS61304A
CS61304A
Percent of
nominal
peak
voltage
120
110
100
90
80
269 ns
244 ns
194 ns
50
10 Nominal Pulse
0
-10
-20
219 ns
488 ns
Figure 9. Mask of the Pulse at the 2048 kbps Interface
Transmit All Ones Select
The transmitter provides for all ones insertion at
the frequency of TCLK. Transmit all ones is se-
lected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or TDATA) inputs are ignored. If Remote
Loopback is in effect, any TAOS request will be
ignored.
Receiver
The receiver extracts data and clock from an AMI
(Alternate Mark Inversion) coded signal and out-
puts clock and synchronized data. The receiver is
sensitive to signals over the entire range of
ABAM cable lengths and requires no equalization
or ALBO (Automatic Line Build Out) circuits.
The signal is received on both ends of a center-
tapped, center-grounded transformer. The
transformer is center tapped on the IC side. The
clock and data recovery circuit exceeds the jitter
tolerance specifications of Publications 43802,
43801, AT&T 62411, TR-TSY-000170, and
CCITT REC. G.823.
A block diagram of the receiver is shown in Fig-
ure 10. The two leads of the transformer (RTIP
and RRING) have opposite polarity allowing the
receiver to treat RTIP and RRING as unipolar sig-
nals. Comparators are used to detect pulses on
RTIP and RRING. The comparator thresholds are
dynamically established at a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0 in-
puts).
The leading edge of an incoming data pulse trig-
gers the clock phase selector. The phase selector
chooses one of the 13 available phases which the
delay line produces for each bit period. The out-
For coaxial cable,
75Ω l o a d a nd
transformer specified
in Application Section.
For shielded twisted
pair, 120Ω load and
transformer specified
in Application Section.
Nominal peak voltage of a mark (pulse)
2.37 V
3V
Peak voltage of a space (no pulse)
0 ±0.237 V
0 ±0.30 V
Nominal pulse width
244 ns
Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval
0.95 to 1.05*
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
0.95 to 1.05*
* When configured with a 0.47 µF nonpolarized capacitor in series with the TX transformer
primary as shown in Figures A1, A2 and A3.
Table 4. CCITT G.703 Specifications
DS156PFP1 2
1111
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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