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PDF MM54HCT190 Data sheet ( Hoja de datos )
| Número de pieza | MM54HCT190 | |
| Descripción | (MM54HCT190 / MM54HCT191) Synchronous Decade Up/Down Counters | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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January 1988
MM54HCT190 MM74HCT190 Synchronous Decade Up
Down Counters with Mode Control MM54HCT191
MM74HCT191 Synchronous Binary Up Down Counters
with Mode Control
General Description
These high speed synchronous counters utilize advanced
silicon-gate CMOS technology They possess the high noise
immunity and low power consumption of CMOS technology
along with the speeds of low power Schottky TTL These
circuits are synchronous reversible up down counters The
MM54HCT191 MM74HCT191 are 4-bit binary counters and
the MM54HCT190 MM74HCT190 are BCD counters
Synchronous operation is provided by having all flip-flops
clocked simultaneously so that the outputs change simulta-
neously when so instructed by the steering logic This mode
of operation eliminates the output counting spikes normally
associated with asynchronous (ripple clock) counters
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input if the
enable input is low A high at the enable input inhibits count-
ing The direction of the count is determined by the level of
the down up input When low the counter counts up and
when high it counts down
These counters are fully programmable that is the outputs
may be preset to either level by placing a low on the load
input and entering the desired data at the data inputs The
output will change independent of the level of the clock in-
put This feature allows the counters to be used as divide by
N dividers by simply modifying the count length with the
preset inputs
Connection Diagram
Dual-In-Line Package
Two outputs have been made available to perform the cas-
cading function ripple clock and maximum minimum count
The latter output produces a high level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows The ripple
clock output produces a low level output pulse equal in
width to the low level portion of the clock input when an
overflow or underflow condition exists The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used or to the clock input if parallel enabling is used The
maximum minimum count output can be used to accom-
plish look-ahead for high speed operation
MM54HCT MM74HCT devices are intended to interface be-
tween TTL and NMOS components and standard CMOS
devices These parts are also plug-in replacements for LS-
TTL devices can be used to reduce power consumption in
existing designs
Features
Y Level changes on Enable or Down Up can be made
regardless of the level of the clock
Y Low quiescent supply current 80 mA maximum
(74HCT Series)
Y Low input current 1 mA maximum
Y TTL compatible inputs
Truth Table
Load
Enable
G
HL
HL
LX
HH
Down
Up
L
H
X
X
Clock Function
u Count Up
u Count Down
X Load
X No Change
Order Number MM54HCT190 191
or MM74HCT190 191
C1995 National Semiconductor Corporation TL F 5744
TL F 5744 – 1
RRD-B30M105 Printed in U S A
Free Datasheet http://www.datasheet4u.com/
1 page  
Timing Diagrams
’HCT190 Synchronous Decade Counters
Typical Load Count and Inhibit Sequences
Sequence
(1) Load (preset) to BCD seven
(2) Count up to eight nine zero one and two
(3) Inhibit
(4) Count down to one zero nine eight and seven
’HCT191 Synchronous Binary Counters
Typical Load Count and Inhibit Sequence
TL F 5744 – 5
Sequence
(1) Load (preset) to binary thirteen
(2) Count up to fourteen fifteen zero one and two
TL F 5744 – 6
(3) Inhibit
(4) Count down to one zero fifteen fourteen and thirteen
5
Free Datasheet http://www.datasheet4u.com/
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MM54HCT190.PDF ] | |
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