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PDF BD8179MUV Data sheet ( Hoja de datos )
| Número de pieza | BD8179MUV | |
| Descripción | 5V Input Multi-channel System Power Supply IC | |
| Fabricantes | ROHM Semiconductor | |
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Power Supply IC Series for TFT-LCD Panels
5V Input Multi-channel
System Power Supply IC
BD8179MUV
No.09035EBT04
●Description
The BD8179MUV is a system power supply IC for TFT panels.
A 1-chip IC providing a total of three voltages required for TFT panels, i.e., source voltage, gate high-level, and gate low-level
voltage, thus constructing a TFT panel power supply with minimal components required.
●Features
1) Step Up DC/DC Converter.
2) Incorporates 18V, 3.0A N-channel FET
3) Linear-Regulator Controllers for VGON and VGOFF
4) 5 channel Operational Amplifiers/±150mA Output Short-Circuit Current 40V / µs Slew Rate
5) Switching Frequency: 1200 kHz.
6) Gate Shading Function Included.
7) Protection Circuits
8) Over Current Protection
9) Timer Latch Mode Short Current Protection.
10) Thermal Shut Down.
11) Under Voltage Protection.
12) Over Voltage Protection
13) VQFN032V5050 Package
●Applications
Liquid crystal TV, PC monitor, and TFT-LCD panel
●Absolute maximum ratings (Ta = 25℃)
Parameter
Symbol
Power Supply Voltage
VIN
VMAIN Voltage
VMAIN
SUP Voltage
VSUP
DRVP Voltage
VDRVP
DRVN Voltage
VDRVN
SRC Voltage
VSRC
CTL Voltage
VCTL
Junction Temperature
Tjmax
Power Dissipation
Pd
Operating Temperature Range
Topr
Storage Temperature Range
Tstg
* Reduced by 19.52 mW/℃ over 25℃, when mounted on a glass epoxy board.
(4-layer 74.2 mm 74.2 mm 1.6 mm).
Limit
7
20
20
40
-30
40
7
150
4560
-40～85
-55～150
Unit
V
V
V
V
V
V
V
℃
mW
℃
℃
●Operating Condition
Parameter
Power Supply Voltage
VMAIN Voltage
SUP Voltage
DRVP Voltage
DRVN Voltage
SRC Voltage
Symbol
VIN
VMAIN
VSUP
VDRVP
VDRVN
VSRC
Limit
Min. Max.
2.6 5.5
8 18
- 18
- 38
- -20
- 38
Unit
V
V
V
V
V
V
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
1/12
2009.07 - Rev.B
Free Datasheet http://www.datasheet4u.com/
1 page  
BD8179MUV
●Pin Assignments Diagram
24 23 22 21 20 19 18 17
FBP
DRVP
FBN
DRVN
DEL
CTL
DRN
COM
25
26
27
28
29
30
31
32
BD8179MUV
16 NEG4
15 POS4
14 SUP
13 OUT3
12 POS3
11 BGND
10 POS2
9 NEG2
1 23 4 56 78
●Block Diagram
VCN
Technical Note
VCP
VIN
IN STEP-UP LX FB
CONTROLLER
COMP
PGND
AGND
SRC
COM
DRN
GATE-ON
CONTROLLER
GATE SHADING
CONTROLLER
DRVP
FBP
DEL
CTL
SUP
NEG1
OUT1 －
OP1
POS1 ＋
NEG2
OUT2 OP－2
POS2 ＋
GATE-OFF
CONTROLLER
DRVN
FBN
REF
REF
NEG4
＋ OUT4
OP4
－ POS4
OP－3
OUT2 ＋
POS3
＋
OP5
－
BGND
NEG5
OUT5
POS5
VMAIN
VCP
VGON
VCN
VGOFF
●Pin Assignments
PIN Pin
NO. Name
Function
PIN Pin
NO. Name
Function
1 SRC Highside Input for Gate Shading switch
17 OUT4 Operational Amplifier 4 Output
2 REF Reference for VGOFF
18 POS5 Operational Amplifier 5 Noninverting Input
3 AGND Ground
19 NEG5 Operational Amplifier 5 Inverting Input
4 PGND Power Ground
20 OUT5 Operational Amplifier 5 Output
5 OUT1 Operational Amplifier 1 Output
21 LX Nch Power MOS FET Drain and Switching Node
6 NEG1 Operational Amplifier 1 Inverting Input
22 IN Power Supply voltage Input
7 POS1 Operational Amplifier 1 Noninverting Input
23 FB Feedback Input for step up DC/DC
8 OUT2 Operational Amplifier 2 Output
24 COMP Error Amplifier Compensation Point for step up DC/DC
9 NEG2 Operational Amplifier 2 Inverting Input
25 FBP Feedback Input for Gate-ON Linear-Regulator
10 POS2 Operational Amplifier 2 Noninverting Input
26 DRVP Gate-ON Linear-Regulator Base Drive
11 BGND Ground
27 FBN Feedback Input for Gate-OFF Linear-Regulator
12 POS3 Operational Amplifier 3 Noninverting Input
28 DRVN Gate-OFF Linear-Regulator Base Drive
13 OUT3 Operational Amplifier 3 Output
29 DEL Delay Input for Gate Shading
14 SUP Power Supply voltage Input for operational Amplifier 30 CTL Switch Control Input for Gate Shading
15 POS4 Operational Amplifier 4 Noninverting Input
31 DRN Lowside Input for Gate Shading switch
16 NEG4 Operational Amplifier 4 Inverting Input
32 COM Gate Shading Output
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
5/12
2009.07 - Rev.B
Free Datasheet http://www.datasheet4u.com/
5 Page 
BD8179MUV
Technical Note
●Notes for use
1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may
result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such
damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special
mode where the absolute maximum ratings may be exceeded is anticipated.
2) GND potential
Ensure a minimum GND pin potential in all operating conditions.
3) Setting of heat
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4) Pin short and mistake fitting
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in
damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the
presence of a foreign object may result in damage to the IC.
5) Actions in strong magnetic field
Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction.
6) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure,
and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process.
7) Ground wiring patterns
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the
GND wiring patterns of any external components.
8) This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of
parasitic elements.For example, when the resistors and transistors are connected to the pins as shown in Fig. 18, a
parasitic diode or a transistor operates by inversing the pin voltage and GND voltage.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result
of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC
malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will
trigger the operation of parasitic elements, such as the application of voltages lower than the GND (P board) voltage to
input and output pins.
(Pin A)
Resistor
(Pin B)
Transistor (NPN)
B
CE
(Pin B)
BC
P+
N
P
P
N
P+
N
Parasitic element
P＋
N
N
P
N
P substrate
GND
P＋
N
(Pin A)
GND
Parasitic elements
GND
Fig.18 Example of a Simple Monolithic IC Architecture
E
GND
Parasitic elements
Parasitic element
GND
9) Overcurrent protection circuits
An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC
destruction that may result in the event of load shorting. This protection circuit is effective in preventing damage due to
sudden and unexpected accidents. However, the IC should not be used in applications characterized by the continuous
operation or transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capability
has negative characteristics to temperatures.
10) Thermal shutdown circuit
This IC incorporates a built-in thermal shutdown circuit for the protection from thermal destruction. The IC should be used
within the specified power dissipation range. However, in the event that the IC continues to be operated in excess of its
power dissipation limits, the attendant rise in the chip's temperature Tj will trigger the thermal shutdown circuit to turn off all
output power elements. The circuit automatically resets once the chip's temperature Tj drops.
Operation of the thermal shutdown circuit presumes that the IC's absolute maximum ratings have been exceeded.
Application designs should never make use of the thermal shutdown circuit.
11) Testing on application boards
At the time of inspection of the installation boards, when the capacitor is connected to the pin with low impedance, be sure
to discharge electricity per process because it may load stresses to the IC. Always turn the IC's power supply off before
connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as
an antistatic measure, and use similar caution when transporting or storing the IC.
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
11/12
2009.07 - Rev.B
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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