PDF SPT7755 Data sheet ( Hoja de datos )

Número de pieza	SPT7755
Descripción	FLASH A/D CONVERTER
Fabricantes	Cadeka
Logotipo
Hay una vista previa y un enlace de descarga de SPT7755 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas
No Preview Available ! SPT7755 8-BIT, 750 MSPS, FLASH A/D CONVERTER OCTOBER 2002 FEATURES • 1:2 Demuxed ECL compatible outputs • Wide input bandwidth – 900 MHz • Low input capacitance – 15 pF • Metastable errors reduced to 1 LSB • Monolithic for low cost • Gray code output APPLICATIONS • Digital oscilloscopes • Transient capture • Radar, EW, ECM • Direct RF down-conversion GENERAL DESCRIPTION The SPT7755 is a full parallel (flash) analog-to-digital con- verter capable of digitizing full scale (0 to –2 V) inputs into eight-bit digital words at an update rate of 750 MSPS. The ECL-compatible outputs are demultiplexed into two sepa- rate output banks, each with differential data ready out- puts to ease the task of data capture. The SPT7755’s wide input bandwidth and low capacitance eliminate the need for external track-and-hold amplifiers for most applications. A proprietary decoding scheme reduces metastable errors to the 1 LSB level. The SPT7755 operates from a single – 5.2 V supply, with a nominal power dissipation of 5.5 W. The SPT7755 is available in an 80-lead surface-mount MQuad package over the industrial temperature range (–25 °C to +85 °C). BLOCK DIAGRAM Analog VRT Input Preamp Comparator 256 CLK CLK CLOCK BUFFER DEMUX CLOCK BUFFER VRM VRB 255 D8 (OVR) D8B D7B 152 D7 D6B (MSB) D5B 151 D4B D6 D3B D2B 128 D5 D1B D0B 127 D4 D8A 64 D3 D7A D6A 63 D5A D2 D4A D3A 2 D1 D2A D1A 1 D0 D0A (LSB) DRB (DATA READY) DRB (DATA READY) D8B (OVR) D7B (MSB) D6B D5B D4B D3B D2B D1B D0B (LSB) DRA (DATA READY) DRA (DATA READY) D8A (OVR) D7A (MSB) D6A D5A D4A D3A D2A D1A D0A (LSB) Free Datasheet http://www.datasheet4u.com/ 1 page TYPICAL INTERFACE CIRCUIT VRBF, VRBS, VRTF, VRTS, VRM (REFERENCE INPUTS) The circuit in figure 1 is intended to show the most elabo- rate method of achieving the least error by correcting for integral linearity, input induced distortion, and power sup- ply/ground noise. This is achieved by the use of external reference ladder tap connections, input buffer, and supply decoupling. Please contact the factory for the SPT7755 evaluation board application note that contains more details on interfacing the SPT7755. The function of each pin and external connections to other components is as follows: VEE, AGND, DGND VEE is the supply pin with AGND as ground for the device. The power supply pins should be bypassed as close to the device as possible with at least a .01 µF ceramic capaci- tor. A 10 µF tantalum can also be used for low frequency suppression. DGND is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and ap- propriately bypassed as shown in figure 1. VIN (ANALOG INPUT) There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by the same source. The SPT7755 is superior to similar de- vices due to a preamplifier stage before the comparators. This makes the device easier to drive because it has con- stant capacitance and induces less slew rate distortion. There are two reference inputs and one external reference voltage tap. These are –2 V (VRB force and sense), mid- tap (VRM) and AGND (VRT force and sense). The refer- ence pins and tap can be driven by op amps as shown in figure 1 or VRM may be bypassed for limited temperature operation. These voltage inputs can be bypassed to AGND for further noise suppression if so desired. Table I – Output Coding VIN D8 D7 . . . D8 >–0.5 LSB 1 10000000 –0.5 LSB 1 10000000 0 10000000 –1.5 LSB 0 10000000 0 10000001 • •• • •• • •• –1.0 V 0 11000000 0 01000000 • •• • •• • •• –2.0 V +0.5 LSB 0 00000001 0 00000000 <(–2.0 V +0.5 LSB) 0 0 0 0 0 0 0 0 0 Indicates the transition between the two codes THERMAL MANAGEMENT The typical thermal impedance is as follows: CLK, CLK (CLOCK INPUTS) ΘCA = +17 °C/W in still air with no heat sink The clock inputs are designed to be driven differentially with ECL levels. The duty cycle of the clock should be kept at 50% to avoid causing larger second harmonics. If this is not important to the intended application, then duty cycles other than 50% may be used. D0 TO D8, DR, DR, (A AND B) The digital outputs can drive 50 Ω to ECL levels when pulled down to –2 V. When pulled down to –5.2 V, the out- puts can drive 130 Ω to 1 kΩ loads. All digital outputs are grey code with the coding as shown in table I. CADEKA rec- ommends using differential receivers on the outputs of the data ready lines to ensure the proper output rise and fall times. We highly recommend that a heat sink be used for this device with adequate air flow to ensure rated performance of the device. We have found that a Thermalloy 17846 heat sink with a minimum air flow of 1 meter/second (200 linear feet per minute) provides adequate thermal perfor- mance under laboratory tests. Application specific condi- tions should be taken into account to ensure that the device is properly heat sinked. SPT7755 5 October 2002 Free Datasheet http://www.datasheet4u.com/ 5 Page

Páginas	Total 8 Páginas
PDF Descargar	[ Datasheet SPT7755.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
SPT7750	8-BIT / 500 MSPS / FLASH A/D CONVERTER	Fairchild Semiconductor
SPT7755	FLASH A/D CONVERTER	Cadeka
SPT7755	FLASH A/D CONVERTER	Fairchild Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar