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PDF SPT7883 Data sheet ( Hoja de datos )
| Número de pieza | SPT7883 | |
| Descripción | 70 MSPS A/D CONVERTER | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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FEATURES
• 2.5 V power supply
• SNR: 60 dB @ƒIN = 10 MHz, ƒS = 70 MHz;
58 dB @ƒIN = 30 MHz
• Low power dissipation: 145 mW @2.5 V;
Sleep mode: 2.6 mW
• Sample rate: 10–115 MSPS
• Frequency-dependent biasing
• Internal sample-and-hold
• Differential input
• Low input capacitance
• 9.67 ENOBs @ ƒIN = 10 MHz, ƒS = 70 MHz
• SFDR: 73 dB
• IP core available
SPT7883
10-BIT, 70 MSPS A/D CONVERTER
PRELIMINARY INFORMATION
APPLICATIONS
NOVEMBER 21, 2001
• Imaging
• Computer scanners
• Communications
• Set top boxes
• Video products
• Battery-operated equipment
• Portable test equipment
GENERAL DESCRIPTION
The SPT7883 is a compact, high-speed, low-power 10-bit
monolithic analog-to-digital converter, implemented in a
0.25 µm CMOS process. It has 10-bit resolution with 9.67
effective bits and spurious-free dynamic range (SFDR) of
73 dB for video frequency signals. The converter includes
a high bandwidth sample-and-hold. The full-scale range
can be set between ±0.5 V and ±1.5 V. It operates from a
single 2.5 V supply. Its low distortion and high dynamic
range provide the performance needed for demanding
imaging, video, and communications applications.
The bias current level for the ADC is automatically ad-
justed based on the clock input frequency. Hence, the
power dissipation of the device is continuously optimized
for the operating frequency.
The SPT7883 has a pipelined architecture, resulting in low
input capacitance. Digital error correction of the 9 most
significant bits ensures good linearity for input frequencies
approaching Nyquist.
The SPT7883 is available in a 28-lead SSOP package
over the industrial temperature range (–40 to +85 °C).
BLOCK DIAGRAM
EXTREF BIAS0 BIAS1
REFP
INP
INN
REFN
CM
CLK
ADC
Clock
Circuit
Digital
Outputs
OE
Free Datasheet http://www.datasheet4u.com/
1 page  
REFERENCES
The SPT7883 can use either an internal or external volt-
age reference. When the digital input EXTREF is high, the
external reference is used. When EXTREF is low, the inter-
nal reference is used.
INTERNAL REFERENCE
The internal references are set at +0.75 V and +1.75 V.
When the internal reference is used, the full-scale range of
the analog input is set at ±1.0 V differential. Do not connect
external references when the internal reference is used.
EXTERNAL REFERENCE
When external references are used, the voltages applied
to the VREF+ and VREF– pins determine the input voltage
range, which is equal to ±(VREF+ – VREF–). Externally gen-
erated reference voltages must be connected to these
pins and should be symmetric about the common mode
voltage (1.2 V).
ANALOG INPUT
The SPT7883 has a differential input that should have a
common mode voltage of 1.2 V. The input voltage range is
determined by the reference voltages, which may be gen-
erated internally or applied externally.
The input of the SPT7883 can be configured in various
ways depending on whether a single-ended or differential,
AC- or DC-coupled input is desired.
AC-coupled input is most conveniently implemented using
a transformer with a center-tapped secondary winding.
The center tap is connected to the CM node, as shown in
figure 1. In order to obtain low distortion, it is important that
the selected transformer does not exhibit core saturation
at full scale. Excellent results are obtained with the Mini-
Circuits T1-6T or T4-6T. Proper termination of the input is
important for input signal purity. A 50 Ω resistor in series
with each input and a small capacitor (typ 27 pF) across
the inputs will attenuate kickback noise from the sample-
and-hold.
If a DC-coupled single-ended input is wanted, a solution
based on operational amplifiers is usually preferred. The
AD8138 is an easy-to-use, single-ended-to-differential
converter. Its data sheet claims –87 dBc @ 20 MHz.
Lower-cost operational amplifiers may be used if the de-
mands are less strict.
CLOCK
In order to preserve accuracy at high input frequency, it is
important that the clock have low jitter and fast rise and fall
times. Rise/fall times should be kept shorter than 2 ns
whenever possible. Overshoot should be minimized. Low
jitter is especially important when converting high-
frequency input signals. Jitter causes the noise floor to rise
proportionally to input signal frequency. The analog input is
sampled at the falling edge of the clock.
Figure 1 – Typical Interface Circuit
AIN
CLK
GND
+A2.5
4.7 +
0.1
VDD
0.1
+A2.5
EXTREF
4.7
+
0.1 0.01
0.1
REFN
REFP
EXTREF
.1
10 +
+ 0.1 0.001 CM
4.7
GND
4.7 0.01
50 +A2.5
+
VDD
T1
50 (T1-6T) or
200 (T4-6T)
27 pF
INN
INP
Mini-Circuits
T1-6T or T4-6T
+A2.5
50
BIAS0
BIAS1
Buffer
CLK
OE
D0
D1
D2
D3
D4
GND
GND
100pF
OVDD
OVDD
D5
D6
D7
D8
D9
50
50
50
50
50
4.7
.1 +
10
+A2.5
50
50
50
50
50
+A2.5
OE
AGND
DGND
FB1
(Ferrite Bead)
5
+D5
SPT7883
11/21/01
Free Datasheet http://www.datasheet4u.com/
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SPT7883.PDF ] | |
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