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PDF SPT8000 Data sheet ( Hoja de datos )
| Número de pieza | SPT8000 | |
| Descripción | CMOS A/D CONVERTER | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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SPT8000
14-BIT, 20 MSPS, CMOS A/D CONVERTER
FEATURES
PRELIMINARY INFORMATION
APPLICATIONS
OCTOBER 12, 2001
• 14-bit, 20 MSPS CMOS analog-to-digital converter
• Excellent performance:
DLE: ±0.5 LSB, ILE: ±1.2 LSB
12.1 Effective Number of Bits @ ƒIN = 5 MHz
SFDR = 87 dB @ ƒIN = 5 MHz
• Internal sample-and-hold and voltage reference
• Power dissipation: 725 mW at 20 MSPS
• +5 V analog supply and +3.3/5 V digital output supply
• Out-of-range indicator
• 44-lead TQFP plastic package
• –40 °C to +85 °C temperature range
• Wireless communications
• IR imaging
• Scanners and digital copiers
• High-end CCD cameras
• Medical imaging
• Automatic test equipment
• Data acquisition systems
• Lab and test equipment
DESCRIPTION
This high-performance, 14-bit analog-to-digital converter
operates at a sample rate of up to 20 MSPS. It utilizes a
digitally calibrated, pipelined CMOS architecture to
achieve excellent dynamic performance and linearity.
Incorporated on chip are a high-performance sample-and-
hold amplifier and internal reference for minimal external
circuitry.
The excellent linearity and superb dynamic performance
of this device make it ideal for image processing and in-
strumentation applications, as well as communications
applications.
The device operates from a single +5 V supply. A separate
digital output supply pin is provided for +3/5 V logic output
levels. Total power dissipation, including internal refer-
ence, is 725 mW. It is in a 44-lead TQFP package over the
industrial temperature range of –40 °C to +85 °C.
BLOCK DIAGRAM AVDD OVDD
VIN+
VIN
SHA
ADC1
MDAC1
ADC2
MDAC2
CLK
VRT
CM
VRC
VBS
MDAC3
ADC3
Reference
&
Buffers
Bias
Generator
Bandgap
VREF/EXTB
ADC4
MDAC4
ADC5
AGND
BGND
OGND
CAL
BUSY
RESETB
14
D13D0 (D0=LSB)
OTR
Free Datasheet http://www.datasheet4u.com/
1 page  
TYPICAL PERFORMANCE CHARACTERISTICS
Performance Versus Input Frequency
95
S = 20 MHz
90
85
80
SFDR
75
THD
70 SNR
SINAD
65
60
0 5 10 15 20 25 30
Input Frequency (MHz)
Performance Versus Temperature
95
S = 20 MHz IN = 5 MHz
90
SFDR
85
THD
80
SNR
75 SINAD
70
65
60
50
25 0
25 50
Temperature (Degrees C)
75
100
Performance Versus Sapmple Rate
95
90 SFDR
IN = 5 MHz
85 THD
80
SNR
SINAD
75
70
65
60
0 5 10 15 20 25 30
Sample Rate (MSPS)
Performance Versus Sample Rate
95
IN = 10 MHz
90
SFDR
85
THD
80
SNR
75 SINAD
SNR
70
SFDR
65 THD
SINAD
60
0 5 10 15 20 25 30
Sample Rate (MSPS)
Differential Linearity Error Versus Code
0.6
0.4
0.2
0.0
0.2
0.4
0.6
0.8
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
Integral Linearity Error Versus Code
1.5
1.0
0.5
0.0
0.5
1.0
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
SPT8000
5 10/12/01
Free Datasheet http://www.datasheet4u.com/
5 Page 
PIN ASSIGNMENTS
AGND
AVDD
N/C
BGND
AVDD
AGND
AVDD
CLK
OGND
OVDD
D0 (LSB)
1
2
3
4
5
6
7
8
9
10
11
SPT8000
33 AGND
32 AVDD
31 N/C
30 BGND
29 AVDD
28 RESETB
27 CAL
26 BUSY
25 OTR
24 D13 (MSB)
23 D12
PIN FUNCTIONS
Name
AGND
AVDD
N/C
BGND
CLK
OGND
OVDD
D0–D13
OTR
BUSY
Description
Ground
+5 V Supply
No Connect. Leave the pin open or tie it to AGND.
Ground
Clock Input
Ground for BUSY, OTR, and Data Bit Outputs
+3.3 V to +5 V Supply for BUSY, OTR, and Data
Bit Outputs
Data Bit Outputs. D0=LSB, D13=MSB
Out of Range Output. OTR goes High for the
Analog input above (overrange) or below
(underrange) the full-scale range. The
corresponding Data Bit Outputs are all 1s for
overrange, and all 0s for underrange.
Busy Output. BUSY goes High when the SPT8000
goes into its internal calibration routine and
remains High until it completes the calibration. The
internal calibration routine takes approximately
74.5 ms for 20 MHz clock input. The SPT8000
ignores the Analog Input when BUSY is High.
When BUSY is Low, it is ready to convert the
Analog Input.
CAL Calibration Start Input. Holding CAL High for more
than two falling edges of CLK, while RESETB is
High, initiates the SPT8000’s internal calibration
routine.
RESETB
Reset Input (active Low). Logic 0 on this
asynchronous reset pin will set the internal digital
state machine to its initial state and clear all
internal calibration coefficients.
VBS Noise Reduction Pin. Connect a noise reduction
capacitor of 4.7 µF or larger from this pin to
AGND.
CM Common Mode Level Output. +2.25 V nominal.
Connect a noise reduction capacitor of 4.7 µF or
larger from this pin to AGND.
VRC Lower Reference. +1.25 V nominal. This voltage
sets the lower bound of analog input span.
Connect a noise reduction capacitor of 4.7 µF or
larger from this pin to AGND.
VRT Upper Reference. +3.25 V nominal. This voltage
sets the upper bound of analog input span.
Connect a noise reduction capacitor of 4.7 µF or
larger from this pin to AGND.
VIN+
Analog Input Pin (+). The nominal span at this pin
is +1.25 V to +3.25 V.
VIN–
Analog Input Pin (–). The nominal span at this pin
is +3.25 V to +1.25 V.
VREF/EXTB Voltage Reference I/O Pin. +1.00 V nominal. The
voltage at this pin sets the span above and below
CM for each analog input pin. Driving VREF/EXTB
to 0 V will disable internal buffers driving VRT and
VRC, allowing the user to drive VRT and VRC
externally. Connect a noise reduction capacitor of
4.7 µF or larger from this pin to AGND.
ORDERING INFORMATION
PART NUMBER
SPT8000SIT
TEMPERATURE RANGE
–40 to +85 °C
PACKAGE
44L TQFP
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR
USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR
THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
www.fairchildsemi.com
© Copyright 2002 Fairchild Semiconductor Corporation
SPT8000
11 10/12/01
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet SPT8000.PDF ] | |
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