|
|
PDF NLSX0102 Data sheet ( Hoja de datos )
| Número de pieza | NLSX0102 | |
| Descripción | Translator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de NLSX0102 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
|
No Preview Available !
NLSX0102
2-Bit 20 Mb/s Dual-Supply
Level Translator
The NLSX0102 is a 2−bit configurable dual−supply bidirectional
auto sensing translator that does not require a directional control pin.
The I/O VCC and I/O VL ports are designed to track two different
power supply rails, VCC and VL respectively. Both the VCC and VL
supply rails are configurable from 1.5 V to 5.5 V. This allows voltage
logic signals on the VL side to be translated into lower, higher or equal
value voltage logic signals on the VCC side, and vice−versa.
The NLSX0102 translator has integrated 10 kW pull−up resistors on
the I/O lines. The integrated pull−up resistors are used to pull−up the
I/O lines to either VL or VCC. The NLSX0102 is an excellent match
for open−drain applications such as the I2C communication bus.
Features
• VL can be Less than, Greater than or Equal to VCC
• Wide VCC Operating Range: 1.5 V to 5.5 V
Wide VL Operating Range: 1.5 V to 5.5 V
• High−Speed with 24 Mb/s Guaranteed Date Rate
• Low Bit−to−Bit Skew
• Enable Input and I/O Pins are
Overvoltage Tolerant (OVT) to 5.5 V
• Non−preferential Power−up Sequencing
• Integrated 10 kW Pull−up Resistors
• Small Space Saving Package
− 1.9 mm x 0.9 mm x 0.5 mm Flipchip8
• This is a Pb−Free Device
Typical Applications
• I2C, SMBus
• Low Voltage ASIC Level Translation
• Mobile Phones, PDAs, Cameras
Important Information
• ESD Protection for All Pins
− Human Body Model (HBM) > 7000 V
http://onsemi.com
A1
FLIP−CHIP 8
CASE 499BF
MARKING
DIAGRAM
A2
AAG
AYWW
A1 D1
AAG
A
Y
WW
= Specific Device Code
= Assembly Location
= Year
= Work Week
PIN ASSIGNMENTS
I/O VCC2
A1 A2 I/O VCC1
GND B1 B2 VCC
VL C1 C2 EN
I/O VL2
D1 D2
(Top View)
I/O VL1
LOGIC DIAGRAM
EN VL VCC GND
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 1
1
Publication Order Number:
NLSX0102/D
Free Datasheet http://www.datasheet4u.com/
1 page  
NLSX0102
Timing Characteristics − Rail−to−Rail Driving Configuration
(I/O test circuits of Figures 2, 3 and 7, CLOAD = 15 pF, driver output impedance ≤ 50 W, RLOAD = 1 MW, unless otherwise specified)
−405C to +855C
Symbol
Parameter
Conditions
VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V
Min Max Min Max Min Max
Unit
VL = 3.0 to 3.6 V
tRVL I/O VL Rise Time
Figure 8
2.3 6.5 1.9 8.0 nS
tRVCC
I/O VCC Rise Time
Figure 8
2.5 6.5 2.1 7.4 nS
tFVL I/O VL Fall Time
Figure 8
2.0 7.2 1.9 5.9 nS
tFVCC
tPHL−VL−VCC
tPLH−VL−VCC
tPHL−VCC−VL
tPLH−VCC−VL
I/O VCC Fall Time
Propagation Delay
(Driving I/O VL, VL to VCC)
Propagation Delay
(Driving I/O VCC, VCC to VL)
Figure 8
Figure 2
Figure 3
2.3 8.0 2.4 9.3 nS
2.4 3.1 nS
3.8 3.8
2.5 2.6 nS
3.6 3.1
tEN Enable Time
tDIS Disable Time
Figure 7
Figure 7
40 35 nS
225 235 nS
tPPSKEW Part−to−Part Skew
0.7 0.7 nS
MDR
Maximum Data Rate
23 24 Mbps
Timing Characteristics – Open Drain Driving Configuration
(I/O test circuits of Figures 4, 5 and 7, CLOAD = 15 pF, driver output impedance ≤ 50 W, RLOAD = 1 MW, unless otherwise specified)
−405C to +855C
VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V
Symbol
Parameter
Conditions
Min Max Min Max Min Max Unit
VL = 1.65 to 1.95 V
tRVL I/O VL Rise Time
Figure 8
38 340 30 245 22.0 134 nS
tRVCC
tFVL
I/O VCC Rise Time
I/O VL Fall Time
Figure 8
Figure 8
34 330 23 218 10.0 120 nS
4.4 11.1 4.3 12.0 4.2 14.2 nS
tFVCC
tPHLVL−VCC
tPLHVL−VCC
I/O VCC Fall Time
Propagation Delay
(Driving I/O VL, VL to VCC)
Figure 8
Figure 2
6.9 11 7.5 16.2 7.0 16.2 nS
2.3 27 2.4 20.0 2.6 23.0 nS
45 260 36.0 208 27.0 208
tPHLVCC−VL
tPLHVCC−VL
Propagation Delay
(Driving I/O VCC, VCC to VL)
Figure 3
1.9 22 1.1 22.0 1.2 22.0 nS
45.0 200 36 150 27.0 112
tEN Enable Time
Figure 7
80 70 35 nS
tDIS
tPPSKEW
Disable Time
Part−to−Part Skew
Figure 7
250 277 290 nS
0.7 0.7 0.7 nS
MDR
Maximum Data Rate
2 2 2 Mbps
http://onsemi.com
5
Free Datasheet http://www.datasheet4u.com/
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet NLSX0102.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NLSX0102 | Translator | ON Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |