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PDF PI49FCT20803 Data sheet ( Hoja de datos )

Número de pieza PI49FCT20803
Descripción (PI49FCT20802 / PI49FCT20803) 1:5/1:7 2.5V Clock Buffer
Fabricantes Pericom Semiconductor 
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Features
ÎÎHigh Frequency >150 MHz
ÎÎHigh-speed, low-noise, non-inverting clock buffer
àà PI49FCT20802 is a 1:5 buffer
àà PI49FCT20803 is a 1:7 buffer
ÎÎLow skew < 150ps
ÎÎLow duty cycle distortion < 300ps
ÎÎLow propagation delay < 3.5ns
ÎÎMultiple VDD, GND pins for noise reduction
ÎÎ2.5V supply voltage and 3V tolerant input
ÎÎPackaging (Pb-free & Green):
àà 16-pin TSSOP (L)
àà 16-pin QSOP (Q) - PI49FCT20802 only
Pin Configuration (PI49FCT20802)
BUF_IN 1
GND 2
CLK0 3
VDD 4
CLK1 5
GND 6
NC 7
VDD 8
16 VDD
15 CLK4
14 CLK3
13 GND
12 CLK2
11 VDD
10 NC
9 GND
Pin Configuration (PI49FCT20803)
BUF_IN 1
GND 2
CLK0 3
VDD 4
CLK1 5
GND 6
CLK2 7
VDD 8
11-0004
16 VDD
15 CLK6
14 CLK5
13 GND
12 CLK4
11 VDD
10 CLK3
9 GND
PI49FCT20802/PI49FCT20803
1:5/1:7 2.5V Clock Buffer for
Networking Applications
Description
The PI49FCT2080x is 2.5V, high-speed, low noise, non-inverting
clock buffer. It is designed to target networking applications that
require low-skew, low-jitter, and high-frequency clock distribu-
tion. It provides output-to-output skew as low as 150ps, and
is an ideal clock distribution device for synchronous systems.
PI49FCT2080x is a clock buffer from a single input that pro-
duces five outputs on PI49FCT20802 and seven outputs on
PI49FCT20803. PI49FCT2080x is characterized for operation
from –40°C to 85°C.
Block Diagram (PI49FCT20802)
CLK0
BUF_IN
CLK1
CLK2
CLK3
CLK4
Block Diagram (PI49FCT20803)
CLK0
BUF_IN
CLK1
CLK2
CLK3
CLK6
1 www.pericom.com
P-0.1
01/24/11

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PI49FCT20803 pdf
PI49FCT20802/PI49FCT20803
1:5/1:7 2.5V Clock Buffer for
Networking Applications
Switching Waveforms
Propagation Delay
Input
Output
tPLH
tR
3V
1.25V
0V
tPHL
VOH
2.0V
1.25V
0.6V
VOL
tF
Pulse Skew – tSK(P)
Input
tPLH
Output
tPHL
tSK(p) = | tPHL – tPLH |
3V
1.5V
0V
VOH
1.5V
VOL
Output Skew – tSK(O)
Input
tPLHx
CLKx
tSK(o)
CLKy
tPLHy
3V
1.5V
tPHLx
0V
VOH
1.5V
VOL
tSK(o)
VOH
1.5V
VOL
tPHLy
tSK(o) = tPLHy – tPLHx or tPHLy – tPHLx
Package Skew – tSK(T)
Input
tPLH1
Package 1
Output
Package 2
Output
tSK(t)
tPLH2
tPHL1
3V
1.5V
0V
VOH
1.5V
VOL
tSK(t)
VOH
1.5V
VOL
tPHL2
tSK(t) = tPLH2 – tPLH1 or tPHL2 – tPHL
11-0004
5 www.pericom.com
P-0.1
01/24/11

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