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PDF MC68LC302 Data sheet ( Hoja de datos )
| Número de pieza | MC68LC302 | |
| Descripción | Low Power Integrated Multiprotocol Processor | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Freescale Semiconductor, Inc.
MC68LC302
Low Power Integrated
Multiprotocol Processor
Reference Manual
For More Information On This Product,
Go to: www.freescale.com
Free Datasheet http://www.datasheet4u.com/
1 page  
Table of Contents
Freescale Semiconductor, Inc.
Paragraph
Number
2.4.4.1.4
2.4.4.1.5
2.4.4.1.6
2.4.4.1.7
2.4.4.1.8
2.4.4.1.9
2.4.4.2
2.4.4.2.1
2.4.4.2.2
2.4.4.2.3
2.4.4.2.4
2.4.4.3
2.4.4.3.5
2.4.4.3.6
2.5
2.6
Title
Page
Number
SLOW_GO Mode...................................................................................2-14
NORMAL Mode......................................................................................2-14
IMP Operation Mode Control Register (IOMCR) ...................................2-14
Low Power Drive Control Register (LPDCR) .........................................2-15
IMP Power Down Register (IPWRD) .....................................................2-15
Default Operation Modes. ......................................................................2-15
Low Power Support................................................................................2-15
Enter the SLOW_GO mode ...................................................................2-15
Entering the STOP/ DOZE/ STAND_BY Mode......................................2-16
IMP Wake-Up from Low Power STOP Modes .......................................2-17
IMP Wake-Up Control Register (IWUCR) ..............................................2-17
Fast Wake-Up ........................................................................................2-18
Ring Oscillator Control Register (RINGOCR) ........................................2-19
Ring Oscillator Event Register (RINGOEVR). .......................................2-20
MC68LC302 Dual Port RAM..................................................................2-20
Internal Registers map...........................................................................2-23
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2
3.2.1
3.2.2
3.3
3.4
3.4.1
3.4.2
3.4.2.1
3.4.2.2
3.4.2.3
3.4.2.4
3.4.2.5
3.4.2.6
3.5
3.5.1
3.5.2
3.5.2.1
3.5.2.2
3.5.2.3
3.5.2.4
Section 3
System Integration Block (SIB)
System Control ........................................................................................3-1
System Control Register (SCR) ...............................................................3-2
System Status Bits...................................................................................3-3
System Control Bits .................................................................................3-3
Freeze Control .........................................................................................3-5
Hardware Watchdog ................................................................................3-5
Programmable Data Bus Size Switch ......................................................3-6
Bus Switch Register (BSR) ......................................................................3-6
Basic Procedure:......................................................................................3-6
Load Boot Code from An SCC.................................................................3-7
DMA Control ..........................................................................................3-10
MC68LC302 Differences........................................................................3-10
IDMA Registers (Independent DMA Controller).....................................3-11
Channel Mode Register (CMR)..............................................................3-11
Source Address Pointer Register (SAPR) .............................................3-13
Destination Address Pointer Register (DAPR).......................................3-13
Function Code Register (FCR) ..............................................................3-13
Byte Count Register (BCR)....................................................................3-13
Channel Status Register (CSR) .............................................................3-13
Interrupt Controller .................................................................................3-14
Interrupt Controller Key Differences.......................................................3-14
Interrupt Controller Programming Model................................................3-14
Global Interrupt Mode Register (GIMR) .................................................3-14
Interrupt Pending Register (IPR)............................................................3-15
Interrupt Mask Register (IMR)................................................................3-16
Interrupt In-Service Register (ISR).........................................................3-16
MC68LC302 REFERENCE MANUAL
For More Information On This Product,
Go to: www.freescale.com
Free Datasheet http://www.datasheet4u.com/
5 Page 
Introduction
Freescale Semiconductor, Inc.
1.2 FEATURES
The features of the LC302 are as follows. The items in bold face type show major differenc-
es from the MC68302, although a complete list of differences is given in 1.4 LC302 Differ-
ences.
• On-Chip Static 68000 Core Supporting a 16- or 8-Bit M68000 Family-System
• SIB Including:
Independent Direct Memory Access (IDMA) Controller.
Interrupt Controller with Two Modes of Operation
Parallel Input/Output (I/O) Ports, some with Interrupt Capability
Parallel Input/Output (I/O) Ports on D15-D8 in 8 bit mode
On-Chip 1152-Byte Dual-Port RAM
Three Timers Including a Watchdog Timer
New Periodic Interrupt Timer (PIT)
Four Programmable Chip-Select Lines with Wait-State Generator Logic
Programmable Address Mapping of the Dual-Port RAM and IMP Registers
On-Chip Clock Generator with Output Signal
On-Chip PLL Allows Operation with 32kHz or 4MHz Crystals
Glueless Interface to EPROM, SRAM, Flash EPROM, and EEPROM
Allows Boot in 8-bit Mode, and Running Switch to 16-bit Mode
System Control:
System Status and Control Logic
Disable CPU Logic (Slave Mode Operation)
Hardware Watchdog
New Low-Power (Standby) Modes With Wake-up From 2 Pins or PIT
Freeze Control for Debugging (Available Only in the PGA Package)
DRAM Refresh Controller
• CP Including:
Main Controller (RISC Processor)
Two Independent Full-Duplex Serial Communications Controllers (SCCs)
Supporting Various Protocols:
High-Level/Synchronous Data Link Control (HDLC/SDLC)
Universal Asynchronous Receiver Transmitter (UART)
Binary Synchronous Communication (BISYNC)
Transparent Modes
Autobaud Support Instead of DDCMP and V.110
Boot from SCC Capability
MC68LC302 REFERENCE MANUAL
For More Information On This Product,
Go to: www.freescale.com
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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