PDF TC58NVG5T2HTA00 Data sheet ( Hoja de datos )

Número de pieza	TC58NVG5T2HTA00
Descripción	32 GBIT (4G X 8 BIT) CMOS NAND E2PROM
Fabricantes	Toshiba
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No Preview Available ! TOSHIBA CONFIDENTIAL TC58NVG5T2HTA00 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 32 GBIT (4G  8 BIT) CMOS NAND E2PROM (Triple-Level-Cell) DESCRIPTION The TC58NVG5T2HTA00 is a single 3.3 V 32 Gbit (40,478,441,472 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192  1024) bytes  516 pages  1064 blocks. The device has one 9216-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 9216-byte increments. The Erase operation is implemented in a single block unit (4128 Kbytes  516 Kbytes:9216 bytes  516 pages). The TC58NVG5T2HTA00 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATURES  Organization Device capacity Register Page size Block size TC58NVG5T2HTA00 9216  516  1064  8 bits 9216  8 9216 bytes (4128K  516K) bytes  Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Multi Page Program, Multi Page Read  Mode control Serial input/output Command control  Number of valid blocks Min 1028 blocks Max 1064 blocks  Power supply VCC  2.7 V to 3.6 V  Access time Cell array to register 150 s max (TBD) Serial Read Cycle 25 ns min  Program/Erase time Auto Page Program Auto Block Erase TBD s/page typ. 3 ms/block typ.  Operating current Read (25 ns cycle) Program (avg.) Erase (avg.) Standby 50 mA max. 50 mA max. 50 mA max. 100 A max.(TBD)  Package TSOP I 48-P-1220-0.50C (Weight: 0.53 g typ.)  FOR RELIABILITY GUIDANCE, PLEASE REFER TO THE APPLICATION NOTES AND COMMENTS (14). 60 bit ECC each 1K bytes required. 1 2011-03-23C Free Datasheet http://www.datasheet4u.com/ 1 page TOSHIBA CONFIDENTIAL TC58NVG5T2HTA00 AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Ta  0 to 70°C, VCC  2.7 V to 3.6 V) SYMBOL PARAMETER tCLS tCLS2 tCLH tCS tCS2 tCH tWP tALS tALH tDS tDH tWC tWH tADL * tWW tRW tRP tRC tREA tCR tCLR tAR tRHOH tRLOH tRHZ tCHZ tCLHZ tREH tIR tRHW tWHC tWHR tWHRS tR tWB tRST CLE Setup Time CLE Setup Time CLE Hold Time CE Setup Time CE Setup Time CE Hold Time Write Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time WE High Hold Time from final address to first data WP High to WE Low Ready to WE Falling Edge Read Pulse Width Read Cycle Time RE Access Time CE Low to RE Low CLE Low to RE Low ALE Low to RE Low Data Output Hold Time from RE High Data Output Hold Time from RE Low RE High to Output High Impedance CE High to Output High Impedance CLE High to Output High Impedance RE High Hold Time Output-High-impedance-to- RE Falling Edge RE High to WE Low WE High to CE Low WE High to RE Low for data output WE High to RE Low for Status & ID Read Memory Cell Array to Starting Address WE High to Busy Device Reset Time (Ready/Read/Program/Erase) MIN MAX UNIT 12  ns 42  ns 10  ns 20  ns 32  ns 10  ns 12  ns 12  ns 10  ns 10  ns 5  ns 25  ns 10  ns 300  ns 100  ns 20  ns 12  ns 25  ns  20 ns 10  ns 10  ns 10  ns 25  ns 5  ns  60 ns  30 ns  30 ns 10  ns 0  ns 30  ns 30  ns 300  ns 180  ns  150(TBD) s  100 ns  10/20/30/200 s * tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 5 2011-03-23C Free Datasheet http://www.datasheet4u.com/ 5 Page TOSHIBA CONFIDENTIAL TC58NVG5T2HTA00 ID Read The device contains ID codes which can be used to identify the device type, the manufacturer, and features of the device. The ID codes can be read out under the following timing conditions: CLE CE tCR WE ALE tAR RE tREA I/O 90h 00h ID Read Address 00 command 98h 1st Data See table 5 2nd Data See table 5 3rd Data See table 5 4th Data See table 5 5th Data See table 5 6th Data Table 5. Code table Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 1st Data Maker Code 10011000 2nd Data 3rd Data Device Code Chip Number, Cell Type 11010111  4th Data Page Size, Block Size, Redundant Size, Organization         5th Data Extended Block  6th Data Technology Code  Hex Data 98h D7h See table See table See table See table 2nd Data Memory Density per each /CE Description 8 Gbits 16 Gbits 32 Gbits 64 Gbits 128 Gbits 256 Gbits I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hex Data 1 1010011 1 1010101 1 1010111 1 1011110 0 0111010 0 0111100 D3h D5h D7h DEh 3Ah 3Ch 3rd Data Internal Chip Number per each CE/ Cell Type Reserved Description 1 2 4 8 2 level cell 4 level cell 8 level cell 16 level cell I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 00 01 10 11 00 01 10 11 0 or 1 0 0 or 1 0 or 1 51 2011-03-23C Free Datasheet http://www.datasheet4u.com/ 11 Page

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