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Número de pieza | MT29F2G16ABBEAHC | |
Descripción | 2Gb NAND Flash Memory | |
Fabricantes | Micron | |
Logotipo | ||
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No Preview Available ! Micron Confidential and Proprietary
2Gb: x8, x16 NAND Flash Memory
Features
NAND Flash Memory
MT29F2G08ABAEAH4, MT29F2G08ABAEAWP, MT29F2G08ABBEAH4
MT29F2G08ABBEAHC, MT29F2G16ABAEAWP, MT29F2G16ABBEAH4
MT29F2G16ABBEAHC
Features
• Open NAND Flash Interface (ONFI) 1.0-compliant1
• Single-level cell (SLC) technology
• Organization
– Page size x8: 2112 bytes (2048 + 64 bytes)
– Page size x16: 1056 words (1024 + 32 words)
– Block size: 64 pages (128K + 4K bytes)
– Plane size: 2 planes x 1024 blocks per plane
– Device size: 2Gb: 2048 blocks
• Asynchronous I/O performance
– tRC/tWC: 20ns (3.3V), 25ns (1.8V)
• Array performance
– Read page: 25µs 3
– Program page: 200µs (TYP: 1.8V, 3.3V)3
– Erase block: 700µs (TYP)
• Command set: ONFI NAND Flash Protocol
• Advanced command set
– Program page cache mode4
– Read page cache mode 4
– One-time programmable (OTP) mode
– Two-plane commands 4
– Interleaved die (LUN) operations
– Read unique ID
– Block lock (1.8V only)
– Internal data move
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Ready/Busy# (R/B#) signal provides a hardware
method of detecting operation completion
• WP# signal: Write protect entire device
• First block (block address 00h) is valid when ship-
ped from factory with ECC. For minimum required
ECC, see Error Management.
• Block 0 requires 1-bit ECC if PROGRAM/ERASE cy-
cles are less than 1000
• RESET (FFh) required as first command after power-
on
• Alternate method of device initialization (Nand_In-
it) after power up (contact factory)
• Internal data move operations supported within the
plane from which data is read
• Quality and reliability
– Data retention: 10 years
• Operating voltage range
– VCC: 2.7–3.6V
– VCC: 1.7–1.95V
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 48-pin TSOP type 1, CPL2
– 63-ball VFBGA
Notes:
1. The ONFI 1.0 specification is available at
www.onfi.org.
2. CPL = Center parting line.
3. See Electrical Specifications – Program/Erase
Characteristics for tR_ECC and tPROG_ECC
specifications.
4. These commands supported only with ECC
disabled.
PDF: 09005aef83b83f42
m69a_2gb_nand.pdf – Rev. H 09/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Free Datasheet http://www.datasheet4u.com/
1 page Micron Confidential and Proprietary
2Gb: x8, x16 NAND Flash Memory
Features
List of Tables
Table 1: Signal Definitions ............................................................................................................................... 8
Table 2: Array Addressing – MT29F2G08 (x8) .................................................................................................. 16
Table 3: Array Addressing – MT29F2G16 (x16) ................................................................................................ 17
Table 4: Asynchronous Interface Mode Selection ........................................................................................... 18
Table 5: Command Set .................................................................................................................................. 29
Table 6: Two-Plane Command Set ................................................................................................................. 30
Table 7: READ ID Parameters for Address 00h ................................................................................................ 34
Table 8: READ ID Parameters for Address 20h ................................................................................................ 35
Table 9: Parameter Page Data Structure ......................................................................................................... 37
Table 10: Feature Address Definitions ............................................................................................................ 42
Table 11: Feature Address 90h – Array Operation Mode .................................................................................. 43
Table 12: Feature Addresses 01h: Timing Mode .............................................................................................. 45
Table 13: Feature Addresses 80h: Programmable I/O Drive Strength ............................................................... 46
Table 14: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 46
Table 15: Status Register Definition ............................................................................................................... 47
Table 16: Block Lock Address Cycle Assignments ............................................................................................ 78
Table 17: Block Lock Status Register Bit Definitions ........................................................................................ 81
Table 18: Error Management Details ............................................................................................................. 100
Table 19: Absolute Maximum Ratings ........................................................................................................... 104
Table 20: Recommended Operating Conditions ............................................................................................ 104
Table 21: Valid Blocks ................................................................................................................................... 104
Table 22: Capacitance .................................................................................................................................. 105
Table 23: Test Conditions ............................................................................................................................. 105
Table 24: DC Characteristics and Operating Conditions (3.3V) ....................................................................... 106
Table 25: DC Characteristics and Operating Conditions (1.8V) ....................................................................... 107
Table 26: AC Characteristics: Command, Data, and Address Input (3.3V) ........................................................ 108
Table 27: AC Characteristics: Command, Data, and Address Input (1.8V) ........................................................ 108
Table 28: AC Characteristics: Normal Operation (3.3V) .................................................................................. 109
Table 29: AC Characteristics: Normal Operation (1.8V) .................................................................................. 109
Table 30: Program/Erase Characteristics ....................................................................................................... 111
PDF: 09005aef83b83f42
m69a_2gb_nand.pdf – Rev. H 09/10 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
5 Page Micron Confidential and Proprietary
2Gb: x8, x16 NAND Flash Memory
Signal Assignments
Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View)
1 2 3 4 5 6 7 8 9 10
A NC NC
NC NC
B NC
NC NC
C WP# ALE Vss CE# WE# R/B#
D Vcc RE# CLE NC NC NC
E NC NC NC NC NC NC
F NC NC NC NC Vss NC
G DNU Vcc LOCK1 I/O13 I/O15 DNU
H I/O8 I/O0 I/O10 I/O12 I/O14 Vcc
J I/O9 I/O1 I/O11 Vcc I/O5 I/O7
K Vss I/O2 I/O3 I/O4 I/O6 Vss
L NC NC
NC NC
M NC NC
NC NC
Note: 1. For the 3V device, G5 changes to DNU. NO LOCK function is available on the 3.3V device.
PDF: 09005aef83b83f42
m69a_2gb_nand.pdf – Rev. H 09/10 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
11 Page |
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