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PDF MGA-43828 Data sheet ( Hoja de datos )
| Número de pieza | MGA-43828 | |
| Descripción | Linear Power Amplifier Module | |
| Fabricantes | AVAGO | |
| Logotipo |  |
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MGA-43828
925–960 MHz Linear Power Amplifier Module
Data Sheet
Description
The Avago MGA-43828 is a fully matched, highly linear
power amplifier (PA) designed for use in the 925-960
MHz band. Based on Avago’s proprietary 0.25um GaAs E-
pHEMT technology, the device features high linearity, gain
and power-added efficiency (PAE) with integrated power
detector and shutdown functions. The MGA-43828 is ideal
for use as a final stage PA for Small Cell base transceiver
station (BTS) applications.
Component Image
(5.0 x 5.0 x 0.9) mm Package Outline
AVAGO
43828
YYWW
XXXX
TOP VIEW
Pin Configuration
Notes:
Package marking provides
orientation and identification
”43828” = Device part number
”YYWW” = Year and work week
”XXXX” = Assembly lot number
Gnd 1
Gnd 2
NC 3
RFin 4
NC 5
Gnd 6
NC 7
(5.0 x 5.0 x 0.9) mm
21 Gnd
20 Gnd
19 RFout
18 RFout
17 RFout
16 Gnd
15 Gnd
Features
• High linearity performance : Max -50dBc ACLR1[1] at 27
dBm linear output power (biased with 5.0V supply)
• High gain : 33 dB
• Good efficiency
• Fully matched
• Built-in detector
• GaAs E-pHEMT Technology[2]
• Low cost small package size: (5.0 x 5.0 x 0.9) mm
• MSL3
• Lead free/Halogen free/RoHS compliance
Specifications
940MHz; 5.0V, Idqtotal =316mA (typ), W-CDMA Test
model #1, 64DPCH downlink signal
• PAE : 14.7%
• 27 dBm linear Pout @ ACLR1 = -50dBc[1]
• 33 dB Gain
• Detector range : 20dB
Applications
• Final stage high linearity amplifier for Picocell and
Enterprise Femtocell PA targeted for small cell BTS
downlink applications.
Note:
1. W-CDMA Test model #1, 64DPCH downlink signal
2. Enhancement mode technology employs positive Vgs, thereby
eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
Functional Block Diagram
Vdd2 Vdd3
Attention: Observe Precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 60 V
ESD Human Body Model = 400 V
Refer to Avago Application Note A004R:
Electrostatic Discharge Damage and Control.
RFin
2nd Stage 3rd Stage
RFout
Biasing Circuit
Vc2 Vc3 VddBias Vdet
Free Datasheet http://www.datasheet4u.com/
1 page  
MGA-43828 typical over-temperature performance at Vc2=3.5V, Vc3=2.8V (Vdd=VddBias=5V) as shown in Figure
25 and Vc2= 3.6V, Vc3=2.5V (Vdd=VddBias=5.5V) unless otherwise stated.
-35 24 -35 24
-40 ACLR1_85°C ACLR1_25°C ACLR1_-40°C
PAE_85°C
PAE_25°C
PAE_-40°C
-45
20 -40 ACLR1_85°C ACLR1_25°C ACLR1_-40°C
PAE_85°C
PAE_25°C
PAE_-40°C
16 -45
20
16
-50 12 -50 12
-55 8 -55 8
-60 4 -60 4
-65 0
19 20 21 22 23 24 25 26 27 28 29 30
Pout/dBm
Figure 10. Over-temperature ACLR1, PAE vs Pout @ 940MHz
Vdd=VddBias=5.0V operating voltage
-65 0
19 20 21 22 23 24 25 26 27 28 29 30
Pout/dBm
Figure 11. Over-temperature ACLR1, PAE vs Pout @ 940MHz
Vdd=VddBias=5.5V operating voltage
-35 24
-40 ACLR1_85°C ACLR1_25°C ACLR1_-40°C
PAE_85°C
PAE_25°C
PAE_-40°C
-45
20
16
-50 12
-55 8
-60 4
-65 0
19 20 21 22 23 24 25 26 27 28 29 30
Pout/dBm
Figure 12. Over-temperature ACLR1, PAE vs Pout @ 957.6MHz
Vdd=VddBias=5.0V operating voltage
-35 24
-40 ACLR1_85°C ACLR1_25°C ACLR1_-40°C
PAE_85°C
PAE_25°C
PAE_-40°C
-45
20
16
-50 12
-55 8
-60 4
-65 0
19 20 21 22 23 24 25 26 27 28 29 30
Pout/dBm
Figure 13. Over-temperature ACLR1, PAE vs Pout @ 957.6MHz
Vdd=VddBias=5.5V operating voltage
1200
1100
Idd_Total_85°C
1000 Idd_Total_25°C
900 Idd_Total_-40°C
800
700
600
500
400
300
19 20 21 22 23 24 25 26 27 28 29 30
Pout/dBm
Figure 14. Over-temperature Idd_Total vs Pout @ 940MHz
Vdd=VddBias=5.0V operating voltage
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
Vdd2 Vdd3
RFoutput
reference
plane
RFin
2nd Stage 3rd Stage
RFout
RFoutput
reference
plane
Biasing Circuit
Vc2 Vc3 VddBias Vdet
Figure 24. RFinput and RFoutput Reference Plane
Demonstration Board Top View (Vdd=VddBias=5.0V, Vc2=3.5V, Vc3=2.8V)
Vdd2 Vdd3
+5V +5V
Vc2=3.5V
VddBias
+5V
Vc3=2.8V
Vdet
(Output)
Pins pointing out of the page
(unit is on top)
1 2 3 4 56
12 11 10 9 8 7
13 14 15 16 17
22 21 20 19 18
Component Value Part Number
C1, C2, C20, C22
56pF +/- 5%
GRM1555C1H056JA01D
C11, C29
0.1uF +/- 10% GRM155R71C104KA88D
C24
82pF +/- 5%
GRM1555C1H820JA01D
C8, C25
2200pF +/- 10% GRM155R71H222KA01D
C7, C13, C28
0.047uF +/- 10% GRM155R71E473KA88D
C9
12pF +/- 5%
GRM1555C1H120JA01D
C26
22nF +/- 10%
CM05X7R223K16AHF
C10 2.2uF +/- 10% GRM21BR71E225KA73L
R1 0Ω RMC1/10 JPTP
R3, R4, R5
0Ω
RMC1/16S JPTH
Note:
For performance optimization control voltage for invidual stages can be adjusted
by varying R2, R3 and R4 resistor value.
Vdd2 Vdd3
+5V +5V
Application board pin header assignments
Pin 1 : Vdd3 (Sense)
Pin 2 : Vdd3 (Force)
Pin 3 : Vdd2 (Sense)
Pin 4 : Vdd2 (Force)
Pin 5 : Vdd1 (Sence) – not used
Pin 6 : Vdd1 (Force) – not used
Pin 13 : Vc1 – not used
Pin 14 : Vc2
Pin 15 : Vc3
Pin 16 : VddBias
Pin 17 : Vdet
Other pins are grounded
Figure 25. Demonstration board application circuit for MGA-43828 module
Vc2=3.5VVc3=2V.d8+VdB5ViasV(Oduettput)
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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