PDF SI3230 Data sheet ( Hoja de datos )

Número de pieza	SI3230
Descripción	PROGRAMMABLE CMOS SLIC
Fabricantes	Silicon Laboratories
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Si3230 PROSLIC® PROGRAMMABLE CMOS SLIC WITH RINGING/BATTERY VOLTAGE GENERATION Features Software Programmable SLIC with codec interface Software programmable internal balanced ringing up to 90 VPK (5 REN up to 4 kft, 3 REN up to 8 kft) Integrated battery supply with dynamic voltage output On-chip dc-dc converter continuously minimizes power in all operating modes Entire solution can be powered from a single 3.3 V or 5 V supply 3.3 V to 35 V dc input range Dynamic 0 V to –94.5 V output Software programmable linefeed parameters: Ringing frequency, amplitude, cadence, and waveshape 2-wire ac impedance constant current feed (20 to 41 mA) Loop closure and ring trip thresholds and filtering Applications Software programmable signal generation and audio processing: DTMF generation and decoding 12 kHz/16 kHz pulse metering generation Phase-continuous FSK (caller ID) generation Dual audio tone generators Smooth and abrupt polarity reversal Extensive test and diagnostic features Realtime dc linefeed measurement GR-909 line test capabilities SPI control interface Extensive programmable interrupts 100% software configurable global solution Lead-Free and RoHS-compliant package options available Interface to Broadcom devices Voice over IP BCM11xx residential gateway BCM3341 VOIP processor BCM33xx cable modem Terminal adapters Fixed cellular terminal Description The Si3230 ProSLIC® is a low-voltage CMOS device that provides a multi-functional subscriber line interface ideal for customer premise equipment (CPE) applications. The ProSLIC integrates subscriber line interface circuit (SLIC) and battery generation functionality into a single CMOS integrated circuit. The integrated battery supply continuously adapts its output voltage to minimize power and enables the entire solution to be powered from a single 3.3 V (Si3230M only) or 5 V supply. The ProSLIC controls the phone line through Silicon Labs’ Si3201 Linefeed IC or discrete circuitry. Si3230 DTMF gfeeanteurraetsionincalnuddedseocfotwdianrge,-caonndfigaurcaobmlep5reRheEnNsivinetesrenat lorfintgeilnegphuopnytosi9g0naVlPinKg, capabilities for operation with only one hardware solution. The ProSLIC is packaged in a 38-pin QFN or TSSOP, and the Si3201 is packaged in a thermally-enhanced 16-pin SOIC. Functional Block Diagram Ordering Information See page 103. Pin Assignments QFN Package NC 1 38 37 36 35 34 33 32 31 FSYNC 2 30 RESET 3 29 SDCH 4 28 SDCL 5 27 VDDA1 6 26 IREF 7 25 CAPP 8 24 QGND 9 23 CAPM 10 22 STIPDC 11 21 SRINGDC 12 13 14 15 16 17 18 19 20 SDITHRU DCDRV DCFF TEST1 GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP Patents pending U.S. Patent #6,567,521 U.S. Patent #6,812,744 Other patents pending INT RESET Si3230 CS SCLK SDO SDI FSYNC PCLK Tone Generators FSK Caller ID Pulse Metering Ringing Generator Loop Closure Detect Ring Trip Detect Line Diagnostics Impedance Synth DTMF Decoder SLIC Linefeed Control Linefeed Monitor DC–DC Converter Controller Linefeed Interface Tip Ring Battery Preliminary Rev. 0.96 7/05 Copyright © 2005 by Silicon Laboratories Si3230 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Free Datasheet http://www.datasheet4u.com/ 1 page Si3230 Table 2. Recommended Operating Conditions Parameter Symbol Test Condition Min* Typ Max* Unit Ambient Temperature Ambient Temperature Si3230 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage TA TA VDDD,VDDA1 ,VDDA2 VDD VBAT K-grade B-grade VBATH = VBAT 0 –40 3.13 3.13 –96 25 25 3.3/5.0 3.3/5.0 — 70 85 5.25 5.0 0 oC oC V V V *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 oC unless otherwise stated. Product specifications are only guaranteed when the typical application circuit (including component tolerances) is used. Table 3. AC Characteristics (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70°C for K-Grade, –40 to 85°C for B-Grade) Parameter Overload Level Audio Tone Generator Signal-to-Distortion Ratio1 Intermodulation Distortion 2-Wire Return Loss Idle Channel Noise3 PSRR from VDDA PSRR from VDDD PSRR from VBAT Test Condition TX/RX Performance THD = 1.5% 0 dBm0, Active off-hook, and OHT, any Zac 200 Hz to 3.4 kHz Noise Performance C-Message Weighted Psophometric Weighted 3 kHz flat RX and TX, DC to 3.4 kHz RX and TX, DC to 3.4 kHz RX and TX, DC to 3.4 kHz Min 2.5 45 — 30 — — — 40 40 40 Typ Max Unit — — VPK — — dB — –45 dB 35 — dB — 15 dBrnC — –75 dBmP — 18 dBrn — — dB — — dB — — dB Notes: 1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching. 2. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking performance in the signal range of 3 dB to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate. 3. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm. 4. Assumes normal distribution of betas. Preliminary Rev. 0.96 5 Free Datasheet http://www.datasheet4u.com/ 5 Page Si3230 Table 10. Switching Characteristics—SPI VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70°C for K-Grade, –40 to 85°C for B-Grade, CL = 20 pF Parameter Symbol Test Conditions Min Typ Max Unit Cycle Time SCLK tc 0.062 — — µsec Rise Time, SCLK tr — — 25 ns Fall Time, SCLK tf — — 25 ns Delay Time, SCLK Fall to SDO Active td1 — — 20 ns Delay Time, SCLK Fall to SDO Transition td2 — — 20 ns Delay Time, CS Rise to SDO Tri-state td3 — — 20 ns Setup Time, CS to SCLK Fall tsu1 25 — — ns Hold Time, CS to SCLK Rise th1 20 — — ns Setup Time, SDI to SCLK Rise tsu2 25 — — ns Hold Time, SDI to SCLK Rise th2 20 — — ns Delay Time between Chip Selects (Continuous SCLK) tcs 440 — — ns Delay Time between Chip Selects (Non-continuous SCLK) tcs 220 — — ns SDI to SDITHRU Propagation Delay td4 — 4 10 ns Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD –0.4 V, VIL = 0.4 V SCLK tr tthru tc tr CS SDI SDO tsu1 tsu2 th2 td1 td2 Figure 2. SPI Timing Diagram th1 tcs td3 Preliminary Rev. 0.96 11 Free Datasheet http://www.datasheet4u.com/ 11 Page

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