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PDF CPC5002 Data sheet ( Hoja de datos )
| Número de pieza | CPC5002 | |
| Descripción | Dual High-Speed Open-Drain Digital Optical Isolator | |
| Fabricantes | IXYS | |
| Logotipo |  |
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INTEGRATED CIRCUITS DIVISION
Features
• Dual Optical Isolator
• Buffers Two Independent Signals
• Power-Down to Hi-Z Doesn't Load Outputs
• Low-Power CMOS Reduces Supply Current
• Output operates Over 2.7V < VDD < 5.5V
• LED Drive Current Only 1.5mA
• High Speed: 10Mbaud Typical
• 3750Vrms Galvanic Isolation
• Single 8-Pin DIP or Surface Mount Package
Applications
• Test and Measurement
• A/D and D/A Isolation
• Power Converter Isolation
• Medical
• Ground Loop Elimination
• I2C Bus Isolation
• Computer Bus Isolation
• Isolated Line Receiver
Approvals
• UL - Pending
• EN/IEC 60950 Certified Component:
TUV Certificate: B 11 10 49410 007
Pb
RoHS
2002/95/EC
e3
Figure 1. CPC5002 Functional Block Diagram
1
A1
2
K1
LED
3
K2
4
A2
LED
CPC5002
Dual High-Speed Open-Drain
Digital Optical Isolator
Description
The CPC5002 is a dual high speed optical logic
isolator with open-drain outputs providing 3750Vrms of
galvanic isolation between the inputs and the outputs.
Activating the input LED causes the open-drain output
to turn on, pulling the voltage of the external pullup
resistor towards ground. Utilizing CMOS technology
enables the output stage’s high-gain circuitry to
operate with a miserly power consumption of <5mW
(typical) when operated with a 3.3V supply voltage
and a low input LED drive current of 1.5mA.
Because optical isolators pass logic levels directly
there is no internal state refresh clock to maintain a
non-changing input. Additionally, the CPC5002 will
always return the buffered signals to their proper value
after a transient interruption at either side.
Ordering Information
Part
CPC5002G
CPC5002GS
CPC5002GSTR
Description
8-Pin DIP (50 / Tube)
8-Pin Surface Mount (50 / Tube)
8-Pin Surface Mount Tape & Reel (1000 / Reel)
8
VDD
7
OUT1
6
OUT2
5
GND
DS-CPC5002-R01
www.ixysic.com
1
Free Datasheet http://www.datasheet4u.com/
1 page  
INTEGRATED CIRCUITS DIVISION
CPC5002
1.9 Switching Specifications
Parameter
Timing Specifications
Clock Frequency
Propagation Delay
Output Falling 1, 3
Output Rising 2, 3
Pulse Width Distortion: |tPLH - tPLH|
Propagation Delay Skew 3
Output Fall Time, 90% to 10%
Conditions
ISINK=6mA, CL=20pF
IF=1.5mA, VDD=3.3V,
RPU=499, CL=20pF,
0.5VIN to 0.5VDD_OUT
As per tPHL and tPLH
As per tPHL and tPLH
IF=1.5mA, VDD=3.3V,
RPU=499, CL=20pF
Symbol Min Typ Max Units
fMAX - 10 - MHz
tPHL 35 81 120 ns
tPLH 35 81 120
PWD
85 ns
tPSK -
- 50 ns
tf 10 15 - ns
Common Mode Specifications
Common Mode Transient Immunity
VOUT = High
VOUT = Low
VCM=20VP-P , VDD=3.3V, TA=25°C
VOUT>2V
VOUT<0.8V
CMH 5 - -
CML 7
-
kV/s
-
1 Falling propagation delay can be reduced by increasing instantaneous LED current drive, typically by increasing CFWD .
2 Rising propagation delay depends on RPU , CL , and IF .
Increasing IF above 2 • ITH (by reducing RS) increases the rising propagation delay.
3 Propagation Delay Skew is the worst case difference propagation delay, High to Low and Low to High between the two channels of a CPC5002
when measured using the test circuit shown below, which is tuned for approximately even rising and falling delays.
1.10 Propagation Delay Test Circuit
27pF
2kΩ
IF
½ CPC5002
VDD
3.3V
VOUT
RPU
499Ω
CL
20pF
R01 www.ixysic.com
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Free Datasheet http://w
5 Page 
INTEGRATED CIRCUITS DIVISION
CPC5002
For the outputs, the CPC5002 is compatible with both SMBus and Fast-mode I2C compatible devices. As with all
mixed type devices on a bus, the weakest driver on that bus determines the minimum value of the pullup resistor.
When the CPC5002 is the only device driving the bus as shown with U1, the minimum E96 standard value for pullup
resistors R5 and R6 will be 511. For bus loading up to 400pF, this pullup resistor value will provide for Fast-mode
compliant I2C bus speeds. At lower data rates or with less capacitive bus loading, the actual resistor value selected
can be higher.
When the CPC5002 shares a bus with another device as is the case with U2, the weakest driver sets the conditions
for selecting the correct resistor value. As stated earlier, the SMBus master is rated as a Low-power device and
therefore is only capable of sinking 350uA to an output low voltage level of 0.4V. A pullup resistor attached to the
maximum supply voltage level of 3.6V and pulled down by this low power driver limits the minimum pullup resistor
value to 9.14k. After considering tolerance and temperature effects the nearest E96 standard value is 9.31k. Most
applications will typically select the more common 10k value for R7 and R8, which allows for a 5% resistor tolerance.
Although shown but not needed in this example are pullup resistors R9 and R10. These resistors, not needed by the
CPC5002 at U2, are utilized whenever the busses they are attached to are also connected to device(s) having logic
level inputs. With heavy loading or excessive leakage on the bus the resistors provide supplementary bias to improve
pullup transition performance and to increase the output logic high level without impacting the LED input current bias
level.
The CPC5002 can be utilized to provide digital isolated buffering in a variety of unique applications. Design support is
available by contacting IXYS Integrated Circuits Division’s Applications.
R01 www.ixysic.com
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