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Número de pieza | CYUSB3035 | |
Descripción | FX3S SuperSpeed USB Controller | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
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No Preview Available ! CYUSB3035
EZ-USB® FX3S SuperSpeed USB Controller
Features
■ Universal serial bus (USB) integration
❐ USB 3.0 and USB 2.0 peripherals compliant with USB 3.0
specification 1.0
❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0
❐ High-speed On-The-Go (HS-OTG) host and peripheral com-
pliant with OTG Supplement Version 2.0
❐ Thirty-two physical endpoints
❐ Support for battery charging Spec 1.1 and accessory charger
adaptor (ACA) detection
■ General Programmable Interface (GPIF™ II)
❐ Programmable 100-MHz GPIF II enables connectivity to a
wide range of external devices
❐ 8- and 16-bit data bus
❐ As many as 16 configurable control signals
■ Mass storage support
❐ SD 3.0 (SDXC) UHS-1
❐ eMMC 4.41
❐ Two ports that can support memory card sizes up to 2TB
■ System I/O expansion with two secure digital I/O (SDIO) ports
■ Native USB-attached storage (UAS), mass-storage class
(MSC), human interface device (HID), full, and Turbo-MTP™
support
■ Fully accessible 32-bit CPU
❐ ARM926EJ core with 200-MHz operation
❐ 512-KB or 256-KB embedded SRAM
■ Additional connectivity to the following peripherals
❐ I2C master controller at 1 MHz
❐ I2S master (transmitter only) at sampling frequencies of
32 kHz, 44.1 kHz, and 48 kHz
❐ UART support of up to 4 Mbps
❐ SPI master at 33 MHz
Logic Block Diagram
■ Selectable clock input frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2-MHz crystal input support
■ Ultra low-power in core power-down mode
❐ Less than 60 µA with VBATT on
❐ 20 µA with VBATT off
■ Independent power domains for core and I/O
❐ Core operation at 1.2 V
❐ I2S, UART, and SPI operation at 1.8 to 3.3 V
❐ I2C operation at 1.2 V
■ 10- × 10-mm, 0.8-mm pitch Pb-free ball grid array (BGA)
package
■ EZ-USB® software and development kit (DVK) for easy code
development
Applications
■ Digital video camcorders
■ Digital still cameras
■ Printers
■ Scanners
■ Video capture cards
■ Test and measurement equipment
■ Surveillance cameras
■ Personal navigation devices
■ Medical imaging devices
■ Video IP phones
■ Portable media players
■ Industrial cameras
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-84160 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 20, 2013
Free Datasheet http://www.datasheet4u.com/
1 page CYUSB3035
OTG Connectivity
In OTG mode, FX3S can be configured to be an A, B, or dual-role
device. It can connect to the following:
■ ACA device
■ Targeted USB peripheral
■ SRP-capable USB peripheral
■ HNP-capable USB peripheral
■ OTG host
■ HNP-capable host
■ OTG device
ReNumeration
Because of FX3S's soft configuration, one chip can take on the
identities of multiple distinct USB devices.
When first plugged into USB, FX3S enumerates automatically
with the Cypress Vendor ID (0x04B4) and downloads firmware
and USB descriptors over the USB interface. The downloaded
firmware executes an electrical disconnect and connect. FX3S
enumerates again, this time as a device defined by the
downloaded information. This patented two-step process, called
ReNumeration, happens instantly when the device is plugged in.
EZ-Dtect
FX3S supports USB Charger and accessory detection
(EZ-Dtect). The charger detection mechanism complies with the
Battery Charging Specification Revision 1.1. In addition to
supporting this version of the specification, FX3S also provides
hardware support to detect the resistance values on the ID pin.
FX3S can detect the following resistance ranges:
■ Less than 10 Ω
■ Less than 1 kΩ
■ 65 kΩ to 72 kΩ
■ 35 kΩ to 39 kΩ
■ 99.96 kΩ to 104.4 kΩ (102 kΩ ± 2%)
■ 119 kΩ to 132 kΩ
■ Higher than 220 kΩ
■ 431.2 kΩ to 448.8 kΩ (440 kΩ ± 2%)
FX3S's charger detects a dedicated wall charger, Host/Hub
charger, and Host/Hub.
VBUS Overvoltage Protection
The maximum input voltage on FX3S's VBUS pin is 6 V. A
charger can supply up to 9 V on VBUS. In this case, an external
overvoltage protection (OVP) device is required to protect FX3S
from damage on VBUS. Figure 4 shows the system application
diagram with an OVP device connected on VBUS. Refer to
Table 7 for the operating range of VBUS and VBATT.
Figure 4. System Diagram with OVP Device For VBUS
POWER SUBSYSTEM
1 OVP device
2
3
4
5
6
7
8
9
GND
VBUS
OTG_ID
SSRX-
SSRX+
SSTX-
SSTX+
D-
D+
EZ-USB FX3S
Carkit UART Mode
The USB interface supports the Carkit UART mode (UART over
D+/D–) for non-USB serial data transfer. This mode is based on
the CEA-936A specification.
In the Carkit UART mode, the output signaling voltage is 3.3 V.
When configured for the Carkit UART mode, TXD of UART
(output) is mapped to the D– line, and RXD of UART (input) is
mapped to the D+ line.
In the Carkit UART mode, FX3S disables the USB transceiver
and D+ and D– pins serve as pass-through pins to connect to the
UART of the host processor. The Carkit UART signals may be
routed to the GPIF II interface or to GPIO[48] and GPIO[49], as
shown in Figure 5 on page 6.
In this mode, FX3S supports a rate of up to 9600 bps.
Document Number: 001-84160 Rev. *B
Page 5 of 50
Free Datasheet http://www.datasheet4u.com/
5 Page CYUSB3035
Table 4. FX3S Input Clock Specifications
Parameter
Phase noise
Maximum frequency deviation
Duty cycle
Overshoot
Undershoot
Rise time/fall time
Description
100-Hz offset
1- kHz offset
10-kHz offset
100-kHz offset
1-MHz offset
Specification
Min Max
– –75
– –104
– –120
– –128
– –130
– 150
30 70
–3
– –3
–3
Units
dB
dB
dB
dB
dB
ppm
%
%
%
ns
32-kHz Watchdog Timer Clock Input
FX3S includes a watchdog timer. The watchdog timer can be
used to interrupt the ARM926EJ-S core, automatically wake up
the FX3S in Standby mode, and reset the ARM926EJ-S core.
The watchdog timer runs a 32-kHz clock, which may be
optionally supplied from an external source on a dedicated FX3S
pin.
The firmware can disable the watchdog timer.
Requirements for the optional 32-kHz clock input are listed in
Table 5.
Table 5. 32-kHz Clock Input Requirements
Parameter
Duty cycle
Frequency deviation
Rise time/fall time
Min Max Units
40 60
%
–
±200
ppm
– 200 ns
Power
FX3S has the following power supply domains:
■ IO_VDDQ: This is a group of independent supply domains for
digital I/Os. The voltage level on these supplies is 1.8 V to 3.3 V.
FX3S provides six independent supply domains for digital I/Os
listed as follows (see Pin Description on page 16 for details on
each of the power domain signals):
❐ VIO1: GPIF II I/O
❐ VIO2: S0-Port Supply
❐ VIO3: S1-Port Supply
❐ VIO4: S1-Port and Low Speed Peripherals (UART/SPI/I2S)
Supply
❐ VIO5: I2C and JTAG (supports 1.2 V to 3.3 V)
❐ CVDDQ: Clock
❐
VsuDpDp:lTyh-visolitsatghee
supply voltage for the logic core.
level is 1.2 V. This supplies the
The nominal
core logic
circuits. The same supply must also be used for the following:
• AVDD: This is the 1.2-V supply for the PLL, crystal oscilla-
tor, and other core analog circuits
• U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt-
ages for the USB 3.0 interface.
■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply for
the USB I/O and analog circuits. This supply powers the USB
transceiver through FX3S's internal voltage regulator. VBATT
is internally regulated to 3.3 V.
Document Number: 001-84160 Rev. *B
Page 11 of 50
Free Datasheet http://www.datasheet4u.com/
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet CYUSB3035.PDF ] |
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