PDF ICS9LPRS464 Data sheet ( Hoja de datos )

Número de pieza	ICS9LPRS464
Descripción	System Clock Chip
Fabricantes	Integrated Device Technology
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DATASHEET System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs ICS9LPRS464 Description ATI RD/RS600 series systems using AMD CPUs Output Features • Integrated Series Resistors on differential outputs • Greyhound Compatible CPU outputs • 2 - 0.7V Low Power differential CPU pairs • 6 - 0.7V Low Power differential SRC pairs • 2 - 0.7V Low Power differential ATIG pairs • 1 - 66 MHz HyperTransport clock • 2 - 48MHz USB clocks • 3 - 14.318MHz Reference clocks Key Specifications • CPU outputs cycle-to-cycle jitter <150ps • SRC outputs cycle-to-cycle jitter < 125ps • ATIG outputs cycle-to-cycle jitter < 125ps • +/- 100ppm frequency accuracy on all outputs if REF is tuned to +/-100ppm Features/Benefits: • 3 - Programmable Clock Request pins for SRC and ATIG clocks • ATIGCLKs are programmable for frequency • Spread Spectrum for EMI reduction • Outputs may be disabled via SMBus • External crystal load capacitors for maximum frequency accuracy Pin Configuration GNDREF 1 56 FS0/REF0 VDDREF 2 55 FS1/REF1 X1 3 54 FS2/REF2 X2 4 VDD48 5 53 *PD 52 VDDHTT 48MHz_0 6 51 HTTCLK0 48MHz_1 7 50 GNDHTT GND48 8 49 CLKREQA# SMBCLK 9 48 CPUKG0T_LPR SMBDAT 10 47 CPUKG0C_LPR RESET_IN# 11 46 VDDCPU SRC5T_LPR 12 45 GNDCPU SRC5C_LPR 13 44 CPUKG1T_LPR VDDSRC 14 43 CPUKG1C_LPR GNDSRC 15 42 VDDA SRC4T_LPR 16 41 GNDA SRC4C_LPR 17 40 NC SRC3T_LPR 18 39 SRC0T_LPR SRC3C_LPR 19 38 SRC0C_LPR SRC2T_LPR 20 37 GNDSRC SRC2C_LPR 21 36 VDDSRC GNDSRC 22 35 ATIG0T_LPR VDDSRC 23 34 ATIG0C_LPR SRC1T_LPR 24 33 VDDATIG SRC1C_LPR 25 32 GNDATIG VDDSRC 26 31 ATIG1T_LPR GNDSRC 27 30 ATIG1C_LPR CLKREQB# 28 29 CLKREQC# 56-Pin SSOP/TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor Power Groups Pin Number VDD 5 GND 8 14,23,26,36 15,22,27,37 33 32 42 41 46 45 52 50 Description USB_48 outputs SRCCLK outputs ATIGCLK differential outputs Analog, PLL CPUCLK8 differential outputs HTTCLK output 21 REF outputs Funtionality FS2 FS1 FS0 000 001 010 011 100 101 110 111 CPU MHz Hi-Z X/2 230.00 240.00 100.00 133.33 166.67 200.00 HTT MHz Hi-Z X/3 76.67 80.00 66.66 66.66 66.66 66.66 SRC M Hz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 ATIG M Hz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 USB M Hz 48.00 48.00 48.00 48.00 48.00 48.00 48.00 48.00 IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 1 1377A—04/07/08 Free Datasheet http://www.datasheet4u.com/ 1 page ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss Absolute Max PARAMETER 3.3V Core Supply Voltage SYMBOL VDD_A CONDITIONS - 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection HBM VDD_In Ts Tambient Tcase ESD prot - - - - - 1Guaranteed by design and characterization, not 100% tested in production. MIN GND - 0.5 -65 0 2000 TYP MAX VDD + 0.5V VDD + 0.5V 150 70 115 UNITS V V °C °C °C V Notes 1 1 1 1 1 1 Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS Notes Input High Voltage Input Low Voltage Input High Current Input Low Current Low Threshold Input- High Voltage Low Threshold Input- Low Voltage Operating Current VIH VIL IIH IIL1 IIL2 VIH_FS 3.3 V +/-5% 2 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VSS - 0.3 -5 -5 VIN = 0 V; Inputs with pull-up resistors -200 3.3 V +/-5% 0.7 VIL_FS IDD3.3OP 3.3 V +/-5% 9LPRS462, all outputs driven 9LPRS464, all outputs driven VSS - 0.3 VDD + 0.3 0.8 5 VDD + 0.3 0.35 200 180 V V uA uA uA V V mA mA 1 1 1 1 1 1 1 1 1 Powerdown Current Input Frequency Pin Inductance Input Capacitance Clk Stabilization Modulation Frequency Tdrive_PD Tfall_PD Trise_PD IDD3.3PD Fi Lpin CIN COUT CINX TSTAB all diff pairs low/low VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or de- assertion of PD to 1st clock Triangular Modulation CPU output enable after PD de-assertion PD fall time of PD rise time of 14.31818 30 21 7 5 6 5 1.8 33 300 5 5 mA MHz nH pF pF pF ms kHz us ns ns 1 2 1 1 1 1 1 1 1 1 1 SMBus Voltage VDD 2.7 5.5 V Low-level Output Voltage Current sinking at VOL = 0.4 V SMBCLK/SMBDAT Clock/Data Rise Time VOL IPULLUP TRI2C @ IPULLUP (Max VIL - 0.15) to (Min VIH + 0.15) 4 0.4 1000 V mA ns SMBCLK/SMBDAT Clock/Data Fall Time TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 1Guaranteed by design and characterization, not 100% tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 1 1 1 1 1 IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 1377A—04/07/08 5 5 Page ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss Table3: ATIG Frequency Selection Table Byte 0 Byte 9 Bit 6 Bit4 Bit3 Bit1 Bit0 ATIG(2:0) Spread ATIG OverClock ATIG ATIG ATIG ATIG ATIG (MHz) SS_EN FS3 FS2 FS1 FS0 % % 0 0 0 0 0 100.00 0 0% 0 0 0 0 1 105.00 0 5% 0 0 0 1 0 110.00 0 10% 0 0 0 1 1 115.00 0 15% 0 0 1 0 0 120.00 0 20% 0 0 1 0 1 125.00 0 25% 0 0 1 1 0 130.00 0 30% 0 0 1 1 1 135.00 0 35% 0 1 0 0 0 100.00 0 0% 0 1 0 0 1 105.00 0 5% 0 1 0 1 0 110.00 0 10% 0 1 0 1 1 115.00 0 15% 0 1 1 0 0 120.00 0 20% 0 1 1 0 1 125.00 0 25% 0 1 1 1 0 130.00 0 30% 0 1 1 1 1 135.00 0 35% 1 000 0 100.00 -0.25% 0% 1 000 1 105.00 -0.25% 5% 1 0 0 1 0 110.00 -0.25% 10% 1 0 0 1 1 115.00 -0.25% 15% 1 0 1 0 0 120.00 -0.25% 20% 1 0 1 0 1 125.00 -0.25% 25% 1 0 1 1 0 130.00 -0.25% 30% 1 0 1 1 1 135.00 -0.25% 35% 1 1 0 0 0 100.00 -0.5% 0% 1 1 0 0 1 105.00 -0.5% 5% 1 1 0 1 0 110.00 -0.5% 10% 1 1 0 1 1 115.00 -0.5% 15% 1 1 1 0 0 120.00 -0.5% 20% 1 1 1 0 1 125.00 -0.5% 25% 1 1 1 1 0 130.00 -0.5% 30% 1 1 1 1 1 135.00 -0.5% 35% IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 11 1377A—04/07/08 11 Page

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