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PDF ADP5050 Data sheet ( Hoja de datos )
| Número de pieza | ADP5050 | |
| Descripción | 5-Channel Integrated Power Solution | |
| Fabricantes | Analog Devices | |
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Data Sheet
5-Channel Integrated Power Solution with Quad
Buck Regulators and 200 mA LDO Regulator
ADP5050
FEATURES
Wide input voltage range: 4.5 V to 15 V
±1.5% output accuracy over full temperature range
250 kHz to 1.4 MHz adjustable switching frequency
Adjustable/fixed output options via factory fuse or I2C interface
I2C interface with interrupt on fault conditions
Power regulation
Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A
sync buck regulators with low-side FET driver
Channel 3 and Channel 4: 1.2 A sync buck regulators
Channel 5: 200 mA low dropout (LDO) regulator
Single 8 A output (Channel 1 and Channel 2 operated in parallel)
Dynamic voltage scaling (DVS) for Channel 1 and Channel 4
Precision enable with 0.8 V accurate threshold
Active output discharge switch
Programmable phase shift in 90° steps
Individual channel FPWM/PSM mode selection
Frequency synchronization input or output
Optional latch-off protection on OVP/OCP failure
Power-good flag on selected channels
Low input voltage detection
Overheat detection on junction temperature
UVLO, OCP, and TSD protection
48-lead, 7 mm × 7 mm LFCSP package
−40°C to +125°C junction temperature
APPLICATIONS
Small cell base stations
FPGA and processor applications
Security and surveillance
Medical applications
GENERAL DESCRIPTION
The ADP5050 combines four high performance buck regulators
and one 200 mA low dropout (LDO) regulator in a 48-lead LFCSP
package that meets demanding performance and board space
requirements. The device enables direct connection to high input
voltages up to 15 V with no preregulators.
Channel 1 and Channel 2 integrate high-side power MOSFETs and
low-side MOSFET drivers. External NFETs can be used in low-side
power devices to achieve an efficiency optimized solution and
deliver a programmable output current of 1.2 A, 2.5 A, or 4 A.
Combining Channel 1 and Channel 2 in a parallel configuration
can provide a single output with up to 8 A of current.
Channel 3 and Channel 4 integrate both high-side and low-side
MOSFETs to deliver output current of 1.2 A.
TYPICAL APPLICATION CIRCUIT
C1
4.5V TO 15V
VREG
VDD
C0
PVIN1
C2
COMP1
EN1
SS12
ADP5050
INT VREG
100mA
OSCILLATOR
CHANNEL 1
BUCK REGULATOR
(1.2A/2.5A/4A)
VREG
SYNC/MODE
RT
FB1
BST1
SW1
C3
DL1 Q1
PGND RILIM1
DL2 RILIM2
PVIN2
C5
COMP2
EN2
CHANNEL 2
BUCK REGULATOR
(1.2A/2.5A/4A)
VREG
SW2
Q2
BST2
FB2
C6
L1
L2
VOUT1
C4
VOUT2
C7
PVIN3
C8
COMP3
EN3
SS34
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PVIN4
C11
COMP4
EN4
1.7V TO 5.5V PVIN5
C14 EN5
VDDIO
SCL
SDA
CHANNEL 3
BUCK REGULATOR
(1.2A)
CHANNEL 4
BUCK REGULATOR
(1.2A)
CHANNEL 5
200mA LDO
REGULATOR
I2C ALERT
BST3
SW3
C9
FB3
PGND3
BST4
SW4
FB4
C12
PGND4
VOUT5
FB5
PWRGD
nINT
L3 VOUT3
C10
L4 VOUT4
C13
VOUT5
C15
EXPOSED PAD
Figure 1.
The switching frequency of the ADP5050 can be programmed
or synchronized to an external clock. The ADP5050 contains a
precision enable pin on each channel for easy power-up sequencing
or adjustable UVLO threshold.
The ADP5050 integrates a general-purpose LDO regulator with
low quiescent current and low dropout voltage that provides up
to 200 mA of output current.
The optional I2C interface provides the user with flexible
configuration options, including adjustable and fixed output
voltage options, junction temperature overheat warning, low
input voltage detection, and dynamic voltage scaling (DVS).
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADP5050
SPECIFICATIONS
VIN = 12 V, VVREG = 5.1 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications,
unless otherwise noted.
Table 1.
Parameter
INPUT SUPPLY VOLTAGE RANGE
QUIESCENT CURRENT
Operating Quiescent Current
UNDERVOLTAGE LOCKOUT
Rising Threshold
Falling Threshold
Hysteresis
OSCILLATOR CIRCUIT
Switching Frequency
Switching Frequency Range
SYNC Input
Input Clock Range
Input Clock Pulse Width
Minimum On Time
Minimum Off Time
Input Clock High Voltage
Input Clock Low Voltage
SYNC Output
Clock Frequency
Positive Pulse Duty Cycle
Rise or Fall Time
High Level Voltage
PRECISION ENABLING
High Level Threshold
Low Level Threshold
Pull-Down Resistor
POWER GOOD
Internal Power-Good Rising Threshold
Internal Power-Good Hysteresis
Internal Power-Good Falling Delay
Rising Delay for PWRGD Pin
Leakage Current for PWRGD Pin
Output Low Voltage for PWRGD Pin
LOGIC INPUTS (SCL AND SDA PINS)
High Level Threshold
Low Level Threshold
LOGIC OUTPUTS
Low Level Output Voltage
SDA Pin
nINT Pin
INTERNAL REGULATORS
VDD Output Voltage
VDD Current Limit
VREG Output Voltage
VREG Dropout Voltage
VREG Current Limit
Symbol
VIN
Min
4.5
Typ
IQ(4-BUCKS)
ISHDN(4BUCKS+LDO)
UVLO
VUVLO-RISING
VUVLO-FALLING
VHYS
3.6
4.8
25
4.2
3.78
0.42
fSW 700 740
250
fSYNC
250
tSYNC_MIN_ON
tSYNC_MIN_OFF
VH(SYNC)
VL(SYNC)
100
100
1.3
fCLK
tCLK_PULSE_DUTY
tCLK_RISE_FALL
VH(SYNC_OUT)
fSW
50http://www.DataSheet4U.com/
10
VVREG
VTH_H(EN)
VTH_L(EN)
RPULL-DOWN(EN)
0.688
0.806
0.725
1.0
VPWRGD(RISE)
VPWRGD(HYS)
tPWRGD_FALL
tPWRGD_PIN_RISE
IPWRGD_LEAKAGE
VPWRGD_LOW
86.3
90.5
3.3
50
1
0.1
50
VLOGIC_HIGH
VLOGIC_LOW
0.7 × VDDIO
VSDA_LOW
VnINT_LOW
VVDD
ILIM_VDD
VVREG
VDROPOUT
ILIM_VREG
3.2
20
4.9
50
3.305
51
5.1
225
95
Max Unit
15.0 V
6.25 mA
65 µA
4.36 V
V
V
780
1400
kHz
kHz
1400
kHz
ns
ns
V
0.4 V
kHz
%
ns
V
0.832
V
V
MΩ
95 %
%
µs
ms
1 µA
100 mV
V
0.3 × VDDIO V
0.4 V
0.4 V
3.4 V
80 mA
5.3 V
mV
140 mA
Test Conditions/Comments
PVIN1, PVIN2, PVIN3, PVIN4 pins
PVIN1, PVIN2, PVIN3, PVIN4 pins
No switching, all ENx pins high
All ENx pins low
PVIN1, PVIN2, PVIN3, PVIN4 pins
RT = 25.5 kΩ
EN1, EN2, EN3, EN4, EN5 pins
IPWRGD = 1 mA
VDDIO = 3.3 V
VDDIO = 3.3 V, ISDA = 3 mA
InINT = 3 mA
IVDD = 10 mA
IVREG = 50 mA
Rev. 0 | Page 5 of 60
5 Page 
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP5050
BST3 1
PGND3 2
SW3 3
PVIN3 4
EN5 5
FB5 6
VOUT5 7
PVIN5 8
PVIN4 9
SW4 10
PGND4 11
BST4 12
ADP5050
TOP
VIEW
(Not to Scale)
36 PVIN1
35 PVIN1
34 SW1
33 SW1
32 BST1
31 DL1
30 PGND
29 DL2
28 BST2
27 SW2
26 SW2
25 PVIN2
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED AND
SOLDERED TO AN EXTERNAL GROUND PLANE.
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1
BST3
High-Side FET Driver Power Supply for Channel 3.
2
PGND3
Power Ground for Channel 3.
3 SW3 Switching Node Output for Channel 3.
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4
PVIN3
Power Input for Channel 3. Connect a bypass capacitor between this pin and ground.
5 EN5 Enable Input for Channel 5. An external resistor divider can be used to set the turn-on threshold.
6 FB5 Feedback Sensing Input for Channel 5.
7
VOUT5
Power Output for Channel 5.
8
PVIN5
Power Input for Channel 5. Connect a bypass capacitor between this pin and ground.
9
PVIN4
Power Input for Channel 4. Connect a bypass capacitor between this pin and ground.
10 SW4
Switching Node Output for Channel 4.
11
PGND4
Power Ground for Channel 4.
12 BST4 High-Side FET Driver Power Supply for Channel 4.
13 nINT
Interrupt Output on Fault Condition. Open-drain output port.
14 EN4
Enable Input for Channel 4. An external resistor divider can be used to set the turn-on threshold.
15
COMP4
Error Amplifier Output for Channel 4. Connect an RC network from this pin to ground.
16 FB4
Feedback Sensing Input for Channel 4.
17
VDDIO
Power Supply for the I2C Interface.
18 SDA
Data Input/Output for the I2C Interface. Open-drain I/O port.
19 SCL
Clock Input for the I2C Interface.
20
PWRGD
Power-Good Signal Output. This open-drain output is the power-good signal for the selected channels.
This pin can be programmed by the factory to set the I2C address of the part; the I2C address setting function
replaces the power-good function on this pin. For more information, see the I2C Addresses section.
21 FB2
Feedback Sensing Input for Channel 2.
22
COMP2
Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground.
23 EN2
Enable Input for Channel 2. An external resistor divider can be used to set the turn-on threshold.
24, 25
PVIN2
Power Input for Channel 2. Connect a bypass capacitor between this pin and ground.
26, 27
SW2
Switching Node Output for Channel 2.
28 BST2 High-Side FET Driver Power Supply for Channel 2.
29 DL2
Low-Side FET Gate Driver for Channel 2. Connect a resistor from this pin to ground to program the current-limit
threshold for Channel 2.
Rev. 0 | Page 11 of 60
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP5050.PDF ] | |
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