|
|
PDF LTC2315-12 Data sheet ( Hoja de datos )
| Número de pieza | LTC2315-12 | |
| Descripción | 5Msps Serial Sampling ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LTC2315-12 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
FEATURES
n 5Msps Throughput Rate
n Guaranteed 12-Bit No Missing Codes
n Internal Reference: 2.048V/4.096V Span
n Low Noise: 73dB SNR
n Low Power: 6.4mA at 5Msps and 5V
n Dual Supply Range: 3V/5V operation
n Sleep Mode with < 1µA Typical Supply Current
n Nap Mode with Quick Wake-up < 1 conversion
n Separate 1.8V to 5V Digital I/O Supply
n High Speed SPI-Compatible Serial I/O
n Guaranteed Operation from –40°C to 125°C
n 8-Lead TSOT-23 Package
APPLICATIONS
n Communication Systems
n High Speed Data Acquisition
n Handheld Terminal Interface
n Medical Imaging
n Uninterrupted Power Supplies
n Battery Operated Systems
n Automotive
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC2315-12
12-Bit, 5Msps Serial
Sampling ADC in TSOT
DESCRIPTION
The LTC®2315-12 is a 12-bit, 5Msps, serial sampling A/D
converter that draws only 6.4mA from a wide range analog
supply adjustable from 2.7V to 5.25V. The LTC2315-12
contains an integrated bandgap and reference buffer which
provide a low cost, high performance (20ppm/°C max)
and space saving applications solution. The LTC2315-12
achieves outstanding AC performance of 72.6dB SINAD
and –84dB THD while sampling a 500kHz input frequency.
The extremely high sample rate-to-power ratio makes the
LTC2315-12 ideal for compact, low power, high speed
systems. The LTC2315-12 also provides both nap and
sleep modes for further optimization of the device power
within a system.
The LTC2315-12 has a high-speed SPI-compatible serial
interface that supports 1.8V, 2.5V, 3V and 5V logic. The
fast 5Msps throughput makes the LTC2315-12 ideally
suited for a wide variety of high speed applications.
Complete 14-/12-Bit Pin-Compatible SAR ADC Family
500ksps 2.5Msps 4.5Msps
5Msps
14-Bit
LTC2312-14 LTC2313-14 LTC2314-14
12-Bit
LTC2312-12 LTC2313-12
LTC2315-12
Power 3V/5V 9mW/15mW 14mW/25mW 18mW/31mW 19mW/32mW
TYPICAL APPLICATION
5V Supply, Internal Reference, 5Msps, 12-bit Sampling ADC
5V
2.2µF
2.2µF
LTC2315-12
VDD CS
REF SCK
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
ANALOG INPUT
0V TO 4.096V
GND
AIN
SDO
OVDD
DIGITAL OUTPUT SUPPLY
1.8V TO 5V
2.2µF
231512 TA01
16k Point FFT, fS = 5Msps, fIN = 500kHz
0 VDD = 5V
–20
SNR = 73.1dBFS
SINAD = 72.6dBFS
THD = –84dB
–40 SFDR = 87dBc
–60
–80
–100
–120
–140
0
500 1000 1500 2000 2500
FREQUENCY (kHz)
231512 TA01a
For more information www.linear.com/LTC2315-12
231512fa
1
1 page  
LTC2315-12
A DC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fSAMPLE(MAX)
fSCK
tSCK
tTHROUGHPUT
tCONV
tACQ
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Maximum Sampling Frequency
Shift Clock Frequency
Shift Clock Period
Minimum Throughput Time, tACQ + tCONV
Conversion Time
Acquisition Time
Minimum CS Pulse Width
SCK Setup Time After CS↓
SDO Enable Time After CS↓
SDO Data Valid Access Time after SCK↓
SCLK Low Time
SCLK High Time
SDO Data Valid Hold Time After SCK↓
SDO into Hi-Z State Time After 16th SCK↓
SDO into Hi-Z State Time After CS↑
CS↑ Setup Time After 14th SCK↓
Latency
(Notes 7, 8)
(Notes 7, 8)
(Note 7)
(Note 7)
(Notes 7, 8)
(Notes 7, 8, 9)
(Notes 7, 8, 9)
(Notes 7, 8, 10)
(Notes 7, 8, 10)
(Note 7)
l5
l 87.5
l 11.4
l 200
l 160
l 40
l5
l5
l 10
l 9.1
l 4.5
l 4.5
l1
l3
10
l3
10
l5
l 1 Cycle Latency
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWAKE_NAP Power-Up Time from Nap Mode
tWAKE_SLEEP Power-Up Time from Sleep Mode
See Nap Mode Section
See Sleep Mode Section
50 ns
1.1 ms
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All voltage values are with respect to ground.
Note 3. When these pin voltages are taken below ground or above VDD
(AIN, REF) or OVDD (SCK, CS, SDO) they will be clamped by internal
diodes. This product can handle input currents up to 100mA below ground
or above VDD or OVDD without latch-up.
Note 4. VDD = 5V, OVDD = 2.5V, fSMPL = 5MHz, fSCK = 87.5MHz, AIN =
–1dBFS and internal reference unless otherwise noted.
Note 5. Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6. Typical RMS noise at code transitions.
Note 7. Parameter tested and guaranteed at OVDD = 2.5V. All input signals
are specified with tr = tf = 1nS (10% to 90% of OVDD) and timed from a
voltage level of OVDD/2.
Note 8. All timing specifications given are with a 10pF capacitance load.
Load capacitances greater than this will require a digital buffer.
Note 9. The time required for the output to cross the VIH or VIL voltage.
Note 10. Guaranteed by design, not subject to test.
Note 11. Recommended operating conditions.
For more information www.linear.com/LTC2315-12
231512fa
5
5 Page 
LTC2315-12
APPLICATIONS INFORMATION
Overview
The LTC®2315-12 is a low noise, high speed, 12-bit succes-
sive approximation register (SAR) ADC. The LTC2315-12
operates over a wide supply range (2.7V to 5.25V) and
provides a low drift (20ppm/°C maximum), internal refer-
ence and reference buffer. The internal reference buffer is
automatically configured to a 2.048V span in low supply
range (2.7V to 3.6V) and to a 4.096V span in the high
supply range (4.75V to 5.25V). The LTC2315-12 samples
at a 5Msps rate and supports an 87.5MHz data clock. The
LTC2315-12 achieves excellent dynamic performance
(73dB SNR, 84dB THD) while dissipating only 32mW from
a 5V supply at the 5Msps conversion rate.
The LTC2315-12 outputs the conversion data with one
cycle of conversion latency on the SDO pin. The SDO pin
output logic levels are supplied by the dedicated OVDD
supply pin which has a wide supply range (1.71V to 5.25V)
allowing the LTC2315-12 to communicate with 1.8V, 2.5V,
3V or 5V systems.
The LTC2315-12 provides both nap and sleep power-down
modes through serial interface control to reduce power
dissipation during inactive periods.
Serial Interface
The LT2315-12 communicates with microcontrollers, DSPs
and other external circuitry via a 3-wire interface. A falling
CS edge starts a conversion and frames the serial data
transfer. SCK provides the conversion clock for the current
sample and controls the data readout on the SDO pin of
the previous sample. CS transitioning low clocks out the
first leading zero and subsequent SCK falling edges clock
out the remaining data as shown in Figures 5, 6 and 7 for
three different timing schemes. Data is serially output MSB
first through LSB last, followed by trailing zeros if further
SCK falling edges are applied. Figure 5 illustrates that dur-
ing the case where SCK is held low during the acquisition
phase, only one leading zero is output. Figures 6 and 7
illustrate that for the SCK held high during acquisition or
continuous clocking mode two leading zeros are output.
Leading zeros allow the 12-bit data result to be framed
with both leading and trailing zeros for timing and data
verification. Since the rising edge of SCK will be coincident
with the falling edge of CS, delay t2 is the delay to the first
falling edge of SCK, which is simply 0.5 • tSCK. Delays t2
(CS falling edge to SCK leading edge) and t10 (14th falling
SCK edge to CS rising edge) must be observed for Figures
5, 6 and 7 and any timing implementation in order for the
conversion process and data readout to occur correctly.
The user can bring CS high after the 14th falling SCK edge
provided that timing delay t10 is observed. Prematurely
terminating the conversion by bringing CS high before
the 14th falling SCK edge plus delay t10 will cause a loss
of conversion data for that sample. The sample-and-hold
is placed in sample mode when CS is brought high. As
shown in Figure 6, a sample rate of 5Msps can be achieved
on the LTC2315-12 by using an 87.5MHz SCK data clock
and a minimum acquisition time of 40ns which results in
the minimum throughput time (tTHROUGHPUT) of 200ns.
Note that the maximum throughput of 5Msps can only be
achieved with the timing implementation of SCK held high
during acquisition as shown in Figure 6.
The LTC2315-12 also supports a continuous data clock
as shown in Figure 7. With a continuous data clock the
acquisition time period and conversion time period must
be designed as an exact integer number of data clock
periods. Because the minimum acquisition time is not an
exact multiple of the minimum SCK period, the maximum
sample rate for the continuous SCK timing is less than
5Msps. For example, a 4.86Msps throughput is achieved
using exactly 18 data clock periods with the maximum data
clock frequency of 87.5MHz. For this particular case, the
acquisition time period and conversion clock period are
designed as 4 data clock periods (TACQ = 45.7ns) and 14
data clock periods (TCONV = 160ns) respectively, yielding
a throughput time of 205.7ns.
For more information www.linear.com/LTC2315-12
231512fa
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LTC2315-12.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LTC2315-12 | 5Msps Serial Sampling ADC | Linear Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |