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PDF LTC2314-14 Data sheet ( Hoja de datos )
| Número de pieza | LTC2314-14 | |
| Descripción | 4.5Msps Serial Sampling ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
n 4.5Msps Throughput Rate
n Guaranteed 14-Bit No Missing Codes
n Internal Reference: 2.048V/4.096V Span
n Low Noise: 77.5dB SNR
n Low Power: 6.2mA at 4.5Msps and 5V
n Dual Supply Range: 3V/5V operation
n Sleep Mode with < 1µA Typical Supply Current
n Nap Mode with Quick Wake-up < 1 conversion
n Separate 1.8V to 5V Digital I/O Supply
n High Speed SPI-Compatible Serial I/O
n Guaranteed Operation from –40°C to 125°C
n 8-Lead TSOT-23 Package
APPLICATIONS
n Communication Systems
n High Speed Data Acquisition
n Handheld Terminal Interface
n Medical Imaging
n Uninterrupted Power Supplies
n Battery Operated Systems
n Automotive
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC2314-14
14-Bit, 4.5Msps Serial
Sampling ADC in TSOT
DESCRIPTION
The LTC®2314-14 is a 14-bit, 4.5Msps, serial sampling A/D
converter that draws only 6.2mA from a wide range analog
supply adjustable from 2.7V to 5.25V. The LTC2314-14
contains an integrated bandgap and reference buffer which
provide a low cost, high performance (20ppm/°C max)
and space saving applications solution. The LTC2314-14
achieves outstanding AC performance of 77dB SINAD and
–85dB THD while sampling a 500kHz input frequency.
The extremely high sample rate-to-power ratio makes the
LTC2314-14 ideal for compact, low power, high speed
systems. The LTC2314-14 also provides both nap and
sleep modes for further optimization of the device power
within a system.
The LTC2314-14 has a high-speed SPI-compatible serial
interface that supports 1.8V, 2.5V, 3V and 5V logic. The
fast 4.5Msps throughput makes the LTC2314-14 ideally
suited for a wide variety of high speed applications.
Complete 14-/12-Bit Pin-Compatible SAR ADC Family
500ksps 2.5Msps 4.5Msps
5Msps
14-Bit
LTC2312-14 LTC2313-14 LTC2314-14
12-Bit
LTC2312-12 LTC2313-12
LTC2315-12
Power 3V/5V 9mW/15mW 14mW/25mW 18mW/31mW 19mW/32mW
TYPICAL APPLICATION
5V Supply, Internal Reference, 4.5Msps, 14-bit Sampling ADC
5V
2.2µF
2.2µF
LTC2314-14
VDD CS
REF SCK
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
ANALOG INPUT
0V TO 4.096V
GND
AIN
SDO
OVDD
DIGITAL OUTPUT SUPPLY
1.8V TO 5V
2.2µF
231414 TA01
32k Point FFT, fS = 4.5Msps, fIN = 500kHz
0 VDD = 5V
–20
SNR = 77.5dBFS
SINAD = 76.9dBFS
–40
THD = 84.9dB
SFDR = 88.1dB
–60
–80
–100
–120
–160
–140
0
250 500 750 1000 1250 1500 1750 2000 2250
FREQUENCY (kHz)
231414 TA01a
For more information www.linear.com/LTC2314-14
231414fa
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1 page  
LTC2314-14
A DC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fSAMPLE(MAX)
fSCK
tSCK
tTHROUGHPUT
tCONV
tACQ
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Maximum Sampling Frequency
Shift Clock Frequency
Shift Clock Period
Minimum Throughput Time, tACQ + tCONV
Conversion Time
Acquisition Time
Minimum CS Pulse Width
SCK Setup Time After CS↓
SDO Enable Time After CS↓
SDO Data Valid Access Time after SCK↓
SCLK Low Time
SCLK High Time
SDO Data Valid Hold Time After SCK↓
SDO into Hi-Z State Time After 16th SCK↓
SDO into Hi-Z State Time After CS↑
CS↑ Setup Time After 14th SCK↓
Latency
(Notes 7, 8)
(Notes 7, 8)
(Note 7)
(Note 7)
(Notes 7, 8)
(Notes 7, 8, 9)
(Notes 7, 8, 9)
(Notes 7, 8, 10)
(Notes 7, 8, 10)
(Note 7)
l 4.5
l 87.5
l 11.4
l 222
l 182
l 40
l 10
l5
l 10
l 9.1
l 4.5
l 4.5
l1
l3
10
l3
10
l5
l 1 Cycle Latency
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWAKE_NAP Power-Up Time from Nap Mode
tWAKE_SLEEP Power-Up Time from Sleep Mode
See Nap Mode Section
See Sleep Mode Section
50 ns
1.1 ms
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All voltage values are with respect to ground.
Note 3. When these pin voltages are taken below ground or above VDD
(AIN, REF) or OVDD (SCK, CS, SDO) they will be clamped by internal
diodes. This product can handle input currents up to 100mA below ground
or above VDD or OVDD without latch-up.
Note 4. VDD = 5V, OVDD = 2.5V, fSMPL = 4.5MHz, fSCK = 87.5MHz, AIN =
–1dBFS and internal reference unless otherwise noted.
Note 5. Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6. Typical RMS noise at code transitions.
Note 7. Parameter tested and guaranteed at OVDD = 2.5V. All input signals
are specified with tr = tf = 1nS (10% to 90% of OVDD) and timed from a
voltage level of OVDD/2.
Note 8. All timing specifications given are with a 10pF capacitance load.
Load capacitances greater than this will require a digital buffer.
Note 9. The time required for the output to cross the VIH or VIL voltage.
Note 10. Guaranteed by design, not subject to test.
Note 11. Recommended operating conditions.
For more information www.linear.com/LTC2314-14
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5 Page 
LTC2314-14
APPLICATIONS INFORMATION
CS
SCK
t3
SDO
tCONV = 15.5 • tSCK + t2 + t10
t10
t2 t6
tCONV
1 2 3 4 14 15 16
t5
0 B13* B12
t4
B11
t7
B0 0
(MSB)
tTHROUGHPUT
tACQ-MIN = 40ns
tACQ-MIN
t9
HI-Z STATE
*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION
Figure 5: LTC2314-14 Serial Interface Timing Diagram (SCK Low During tACQ)
231414 F05
CS tCONV(MIN) = 15 • tSCK + t2 + t10
t2 t6 tCONV
SCK
1 234 5
t10
15 16
tACQ-MIN = 40ns
tACQ-MIN
t5
t3
t4 t7
t9
SDO
00
B13* B12
B11
B1 B0 0
HI-Z STATE
(MSB)
tTHROUGHPUT
*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION
231414 TD06
Figure 6: LTC2314-14 Serial Interface Timing Diagram (SCK High During tACQ)
CS
t2
tCONV = 16 • tSCK
t6 tCONV
t10
tACQ = 4 • tSCK
tACQ
SCK 20 1 2 3 4 5
15 16 17 18 19
t5
t3
t4 t7
t9
SDO
00
B13* B12
B11
B1 B0 0
(MSB)
tTHROUGHPUT = 20 • tSCK
HI-Z STATE
*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION
Figure 7: LTC2314-14 Serial Interface Timing Diagram (SCK Continuous)
20
231414 TD07
For more information www.linear.com/LTC2314-14
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11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LTC2314-14.PDF ] | |
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