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PDF MAX16997 Data sheet ( Hoja de datos )

Número de pieza MAX16997
Descripción (MAX16997 / MAX16998) High-Voltage Watchdog Timers
Fabricantes Maxim Integrated Products　
Logotipo Maxim Integrated Products Logotipo



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19-4000; Rev 1; 4/09
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
General Description
The MAX16997/MAX16998 are microprocessor (µP)
supervisory circuits for high-input-voltage and low-qui-
escent-current applications. These devices detect
downstream circuit failures and provide switchover to
redundant circuitry. See the Selector Guide for the dif-
ferent versions of this product family.
The MAX16997/MAX16998 family has four independent
inputs for reset and watchdog functions. SWT and SRT
inputs independently set the timeout periods of watch-
dog and reset timers through external capacitors.
RESETIN/EN monitor voltages at respective inputs. A
resistive voltage-divider sets the reset threshold.
The MAX16998A/B/D generate two output signals,
RESET and ENABLE. RESET asserts whenever
RESETIN drops below its threshold voltage or when the
watchdog timer detects a timing fault at WDI. Once
asserted, and after all reset conditions are removed,
RESET remains low for the reset timeout period, tRESET,
and then goes high. The MAX16997A generates one
output signal (ENABLE) based on the voltage level at
EN and the signal at WDI.
The MAX16997A does not have a RESET output. The
watchdog is disabled if the voltage at EN is below its
threshold. The MAX16997A watchdog timer starts tim-
ing when the voltage at EN becomes higher than the
preset threshold voltage level. Each time EN rises
above the preset threshold voltage, the initial watchdog
timeout period is 8 times the normal watchdog timeout
period (tWP).
The MAX16997/MAX16998 are available in 8-pin lead-
free µMAX® packages and are fully specified over the
-40°C to +125°C automotive temperature range.
Automotive
Industrial
Applications
Features
o Wide 5V to 40V Input Voltage Range
o 18µA Quiescent Current (Typical at +125°C)
o Capacitor-Adjustable Timeout Period for
Watchdog and Reset
o Windowed Watchdog Timer Options
(MAX16998B/D)
o External Voltage Monitoring (RESETIN for the
MAX16998A/B/D and EN for the MAX16997A)
o Car Battery-Compatible EN Input
o TTL- and CMOS-Compatible Open-Drain Outputs
o 18V Maximum Open-Drain Reset Output Voltage
o 28V Maximum Open-Drain Enable Output Voltage
o Power-On/Power-Off Reset Functionality
(MAX16998A/B/D Only)
o AECQ-100 Qualified
o -40°C to +125°C Operating Temperature Range
o Small (3mm x 3mm) µMAX Package
http://www.DataSheet4U.net/
o WDI Narrow Pulse Immunity
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX16997AAUA+
-40°C to +125°C 8 µMAX
MAX16998AAUA+
-40°C to +125°C 8 µMAX
MAX16998BAUA+
-40°C to +125°C 8 µMAX
MAX16998DAUA+
-40°C to +125°C 8 µMAX
+Denotes a lead(Pb)-free/RoHS-compliant package.
Selector Guide
PART
WATCHDOG
WINDOW SIZE (%)
ENABLE
MAX16997A
MAX16998A
100
100
✓
✓
MAX16998B
MAX16998D
50
75
✓
✓
Pin Configurations appear at end of data sheet.
RESET
—
✓
✓
✓
EN RESETIN
✓—
—✓
—✓
—✓
µMAX is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

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MAX16997 pdf
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
Pin Description
PIN
MAX16997A MAX16998A/B/D
11
2—
3, 7 —
44
55
66
88
—2
—3
—7
NAME
FUNCTION
IN
EN
N.C.
Power-Supply Input. Bypass IN to GND with a 0.1µF capacitor.
High-Impedance Input to the Enable Comparator. Depending on the voltage level
at EN, the internal watchdog timer is turned on or off (see the EN Input section).
No Connection. Not internally connected.
SWT
Watchdog Timeout Adjustment Input. Connect a capacitor between SWT and GND
to set the basic watchdog timeout period. Connect SWT to ground to disable the
watchdog timer function. See the Selecting the Watchdog Timeout Capacitor
section.
GND
WDI
ENABLE
Ground
Watchdog Input.
MAX16997A/MAX16998A (Timeout Watchdog): Two consecutive WDI falling
edges must occur at WDI within the watchdog timeout period or RESET asserts.
The watchdog timer clears when a falling edge occurs on WDI or whenever RESET
is asserted. ENABLE asserts if three consecutive watchdog timeout periods have
expired without a falling edge at WDI. WDI is a high-impedance input. Leaving
WDI unconnected will cause improper operation of the watchdog timer.
MAX16998B/D (Window Watchdog): WDI falling transitions within periods shorter
than the closed window width or longer than the basic watchdog timeout period
force RESET to assert low for the reset timeout period. The watchdog timer begins
to count after RESET ishttp://www.DataSheet4U.net/ deasserted. The watchdog timer clears when a WDI falling
edge occurs or whenever RESET is asserted. ENABLE asserts if three consecutive
watchdog timeout periods have expired without a falling edge at WDI. WDI is a
high-impedance input. Leaving WDI unconnected will cause improper operation of
the watchdog timer.
Open-Drain Enable Output. ENABLE asserts when three consecutive WDI faults
occur. ENABLE remains low until three consecutive good WDI falling edges occur.
ENABLE does not assert if the voltage at RESETIN (EN) is below its threshold.
These devices are guaranteed to be in correct ENABLE output logic state when
VIN remains greater than 1.1V.
RESETIN
Reset Input. High-impedance input to the reset comparator. When VRESETIN falls
below 1.235V, RESET asserts. RESET remains asserted as long as VRESETIN is low
and for the reset timeout period after RESETIN goes high. Connect VRESETIN to the
center point of an external resistive divider to set the threshold for the externally
monitored voltage. Connect RESETIN to a defined voltage logic-level.
Reset Timeout Adjustment Input. Connect a capacitor between SRT and GND to
SRT set the reset timeout period. See the Selecting the Reset Timeout Capacitor
section.
RESET
Open-Drain Reset Output. RESET asserts whenever RESETIN drops below the
selected reset threshold voltage (VPON). RESET remains low for the reset timeout
period after all reset conditions are removed, and then goes high. RESET asserts
for a period of tRESET whenever a WDI fault occurs. Connect RESET to a pullup
resistor connected to a voltage higher than 2.5V (typ).
_______________________________________________________________________________________ 5

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MAX16997 arduino
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
RESETIN Input (MAX16998A/B/D)
The MAX16998A/B/D monitor the voltage at RESETIN
using an adjustable reset threshold, set with an external
resistive divider (see Figure 7). RESET asserts when
VRESETIN is below 1.235V.
Use the following equations to calculate the externally
monitored voltage (VCC).
VTH
=
VPON
⎡
⎢
⎣
R1
R2
+
⎤
1⎥
⎦
VCC
R1
R2
VIN
MAX16998A/B/D
RESETIN
where VTH is the desired reset threshold voltage, and
VPON = 1.235V. To simplify the resistor selection,
choose a value for R2 (< than 1MΩ) and calculate R1.
Figure 7. Setting RESETIN Voltage for the MAX16998A/B/D
R1
=
R2
⎡
⎢
⎣
VTH
VPON
⎤
− 1⎥
⎦
EN Input
The MAX16997A provides a high-impedance input (EN)
to the enable comparator. Based on the voltage level at
EN, the watchdog timer is turned on or off. The watch-
dog timer starts timing if the voltage level at EN is high-
er than a preset threshold voltage (VPON). Each time
the voltage at EN rises from below to above the preset
threshold voltage, the initial watchdog timeout period is
8 times the normal watchdog timeout period (tWP).
Watchdog Timer
MAX16997A
The watchdog circuit monitors the µC’s activity. For the
MAX16997A, the watchdog timer starts timing once the
voltage at EN is higher than a preset threshold voltage.
ENABLE asserts if three consecutive watchdog timeout
periods have elapsed without a falling edge at WDI.
ENABLE remains low until three consecutive WDI falling
edges with periods shorter than the watchdog timeout
period occur.
Each time the voltage at EN rises from below to above
the preset threshold voltage, the first watchdog timeout
period extends by a factor of 8 (8 x tWP). If a WDI falling
edge occurs during that time, then the watchdog time-
out period is immediately switched over to a single tWP.
If no watchdog falling edge occurs during this pro-
longed watchdog timeout period, ENABLE goes low at
the end of this period and stays low. After this, the first
falling edge at WDI switches the watchdog timeout
period to a single tWP. See Figure 1. The MAX16997A
watchdog timeout period (tWP) is adjustable by a single
capacitor at SWT.
MAX16998A
The MAX16998A asserts RESET when two consecutive
WDI falling edges do not occur within the adjusted
watchdog timeout period (tWP). RESET remains assert-
ed for the reset timeout period (tRESET) and then goes
high. This device also asserts ENABLE if three consec-
utive watchdog timeout periods have elapsed without a
falling edge at WDI. ENABLE remains low until three
consecutive WDI falling edges with periods shorter
than the watchdog timeout period occur (see Figure 2).
http://www.DataSheet4U.net/
The internal watchdog timer is cleared by a RESET ris-
ing edge or by a falling edge at WDI. The watchdog
timer remains cleared while RESET is asserted; as soon
as RESET is released, the timer starts counting. WDI
falling edges are ignored when RESET is low. If no WDI
falling edge occurs within the watchdog timeout period,
RESET immediately goes low and stays low for the
adjusted reset timeout period.
MAX16998B/D
The MAX16998B/D have a windowed watchdog timer.
The watchdog timeout period (tWP) is the sum of a
closed window period (tCW) and an open window period
(tOW). If the µC issues a WDI falling edge within the open
window period, RESET stays high. Once a WDI falling
edge occurs within the closed window period, RESET
immediately goes low and stays low for the adjusted
reset timeout period (see Figure 3). If no WDI falling
edge occurs within the watchdog timeout period, RESET
immediately goes low and stays low for the adjusted
reset timeout period. The open window size is factory-set
to 50% of the watchdog timeout period for the
MAX16998B and 75% for the MAX16998D.
Figure 8 shows a WDI falling edge identified as a good or
a bad WDI signal edge. In case 1, the WDI falling edge
occurs within the closed window period and is considered
a bad WDI falling edge (early fault); therefore, it asserts
RESET. Case 2 also shows another fault. In this case, no
______________________________________________________________________________________ 11

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