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PDF K8P5616UZB Data sheet ( Hoja de datos )
| Número de pieza | K8P5616UZB | |
| Descripción | 256Mb B-die Page NOR FLASH | |
| Fabricantes | Samsung semiconductor | |
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Rev. 1.0, Jun. 2010
K8P5616UZB
256Mb B-die Page NOR FLASH
256M Bit (16M x16, 32M x8), Page Mode
datasheet
http://www.DataSheet4U.net/
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
-1-
datasheet pdf - http://www.DataSheet4U.net/
1 page  
K8P5616UZB
datasheet
Rev. 1.0
NOR FLASH MEMORY
256M Bit (16M x16, 32Mb x8) Page Mode / Page NOR Flash Memory
1.0 FEATURES
2.0 GENERAL DESCRIPTION
• Single Voltage, 2.7V to 3.6V for Read and Write operations
Voltage range of 2.7V to 3.1V valid for MCP product
• Organization
16M x16 bit (Word mode)
32M x 8 bit (Byte mode)
• Fast Read Access Time : 80ns
• Page Mode Operation
8 Words Page access allows fast asychronous read
Page Read Access Time : 30ns
• Read While Program/Erase Operation
• Multiple Bank Architecture (4 Banks)
Bank 0: 32Mbit (64Kw x 32)
Bank 1: 96Mbit (64Kw x 96)
Bank 2: 96Mbit (64Kw x 96)
Bank 3: 32Mbit (64Kw x 32)
• OTP Block : Extra 256 word
- 128word for factory and 128word for customer OTP
• Power Consumption (typical value)
- Active Read Current : 30mA (@5MHz)
- Program/Erase Current : 25mA
- Read While Program or Read While Erase Current : 65mA
- Standby Mode/Auto Sleep Mode : 20uA
• Support Single & 32word Buffer Program
• WP/ACC input pin
- Allows special protection of first or last block of flash array at VIL,
regardless of block protect status
- Removes special protection at VIH, the first or last block of flash array
return to normal block protect status
- Reduce program time at VHH : 6us/word at Write Buffer
• Erase Suspend/Resume
• Program Suspend/Resume
• Unlock Bypass Mode
• Hardware RESET Pin
• Command Register Operation
• Supports Common Flash Memory Interface
• Industrial Temperature : -40°C to 85°C
• Extended Temperature : -25°C to 85°C
• Endurance : 100Kcycle
• Vio options at 1.8V and 3V I/O
• Package options
- 56 Pin TSOP (20x14mm)
- 64 Ball FBGA (11x13, 1.0mm Ball Pitch)
The K8P5616UZB featuring single 3.0V power supply, is an 256Mbit NOR-
type Flash Memory organized as 32M x 8 or 16M x16. The memory archi-
tecture of the device is designed to divide its memory arrays into 256 blocks
with independent hardware protection. This block architecture provides
highly flexible erase and program capability. The K8P5616UZB NOR Flash
consists of four banks. This device is capable of reading data from one
bank while programming or erasing in the other banks.
The K8P5616UZB offers page access time of 30ns with random access
time of 80ns. The device′s fast access times allow high speed microproces-
sors to operate without wait states. The device performs a program opera-
tion in unit of 16 bits (Word) and erases in units of a block. Single or multiple
blocks can be erased. The block erase operation is completed within typi-
cally 0.7 sec. The device requires 25mA as program/erase current in the
commercial and extended temperature ranges.
The K8P5616UZB NOR Flash Memory is created by using Samsung's
advanced CMOS process technology. This device is available in 64FBGA
and 56 Pin TSOP. The device is compatible with EPROM applications to
require high-density and cost-effective nonvolatile read/write storage solu-
tions.
http://www.DataSheet4U.net/
-5-
datasheet pdf - http://www.DataSheet4U.net/
5 Page 
K8P5616UZB
datasheet
Rev. 1.0
NOR FLASH MEMORY
9.0 COMMAND DEFINITIONS
The K8P5616UZB operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a cer-
tain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which
include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences are
stated in Table 5.
[Table 5] Command Sequences (x16)
Command Sequence
Cycle 1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
6th Cycle
Read
Addr
Data
1
RA
RD
Reset
Addr
Data
1
XXXH
F0H
Autoselect Manufacturer ID
1), 2)
Addr
Data
4
555H
AAH
2AAH
55H
(DA)555H
90H
(DA)X00H
ECH
Autoselect Device ID 1), 2), 3)
Addr
Data
6
555H
AAH
2AAH
55H
(DA)555H
90H
(DA)X01H
227EH
(DA)X0EH
2264H
(DA)X0FH
2260H
Autoselect Block Protect Verify Addr
1), 2)
Data
4
555H
AAH
2AAH
55H
(DA)555H
90H
BA / X02H
(SeeTable6)
Autoselect Indicator Bit 1), 2)
Addr
Data
4
555H
AAH
2AAH
55H
(DA)555H
90H
(DA)X03H
(See Table 6)
Autoselect Master Locking Bit Addr
1), 2)
Data
4
555H
AAH
2AAH
55H
(DA)555H
90H
(DA)X07H
(See Table 6)
Program
Addr
Data
4
555H
AAH
2AAH
55H
555H
A0H
PA
PD
Write to Buffer 4)
Addr
Data
6
555H
AAH
2AAH
55H
BA
25H
BA
WC
WBL
PD
WBL
PD
Program Buffer to Flash
Addr
Data
1
BA
29H
Write to Buffer Abort Reset4)
Addr
Data
3
555H
AAH
2AAH
http://www.DataSheet4U.net/
55H
555H
F0H
Unlock Bypass
Addr
Data
3
555H
AAH
2AAH
55H
555H
20H
Unlock Bypass
Program
Addr
Data
2
XXXH
A0H
PA
PD
Unlock Bypass Block Erase Addr
Data
2
XXXH
80H
BA
30H
Unlock Bypass Chip Erase
Addr
Data
2
XXXH
80H
XXXH
10H
Unlock Bypass Reset
Addr
Data
2
XXXH
90H
XXXH
00H
Chip Erase
Addr
Data
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
555H
10H
Block Erase
Addr
Data
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
BA
30H
Block Erase Suspend 5), 6)
Addr
Data
1
(DA)XXXH
B0H
Block Erase Resume
Addr
Data
1
(DA)XXXH
30H
- 11 -
datasheet pdf - http://www.DataSheet4U.net/
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