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PDF LTC2271 Data sheet ( Hoja de datos )
| Número de pieza | LTC2271 | |
| Descripción | 20Msps Serial Low Noise Dual ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2271 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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FEATURES
n 2-Channel Simultaneous Sampling ADC
n Serial LVDS Outputs: 1, 2 or 4 Bits per Channel
n 84.1dB SNR (46μVRMS Input Referred Noise)
n 99dB SFDR
n Low Power: 185mW Total
n 92mW per Channel
n Single 1.8V Supply
n Selectable Input Ranges: 1VP-P to 2.1VP-P
n 200MHz Full-Power Bandwidth S/H
n Shutdown and Nap Modes
n Serial SPI Port for Configuration
n Pin Compatible With
LTC2190: 16-Bit, 25Msps, 104mW
n 52-Lead (7mm × 8mm) QFN Package
APPLICATIONS
n Low Power Instrumentation
n Software-Defined Radios
n Portable Medical Imaging
n Multi-Channel Data Acquisition
LTC2271
16-Bit, 20Msps
Serial Low Noise Dual ADC
DESCRIPTION
The LTC®2271 is a 2-channel, simultaneous sampling
16-bit A/D converter designed for digitizing high frequency,
wide dynamic range signals. It is perfect for demanding
communications applications with AC performance that
includes 84.1dB SNR and 99dB spurious free dynamic
range (SFDR).
DC specs include ±1LSB INL (typ), ±0.2LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.44LSBRMS.
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs one bit, two bits or
four bits at a time. The LVDS drivers have optional internal
termination and adjustable output levels to ensure clean
signal integrity.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs.www.DataSheet.net/ An internal clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
CH1
ANALOG
INPUT
CH2
ANALOG
INPUT
ENCODE
INPUT
S/H
S/H
1.8V
VDD
16-BIT
ADC CORE
16-BIT
ADC CORE
PLL
GND
1.8V
OVDD
DATA
SERIALIZER
OGND
2271 TA01
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
DATA CLOCK OUT
FRAME
SERIALIZED
LVDS
OUTPUTS
Integral Non-Linearity (INL)
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0
16384 32768 49152 65536
OUTPUT CODE
2271 TA02
2271f
1
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
LTC2271
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
Single-Ended Encode Mode (ENC– Tied to GND)
CONDITIONS
MIN TYP MAX UNITS
VIH High Level Input Voltage
VDD =1.8V
l 1.2
VIL Low Level Input Voltage
VIN Input Voltage Range
VDD =1.8V
ENC+ to GND
l
l0
0.6
3.6
RIN Input Resistance
See Figure 11
30
CIN Input Capacitance
(Note 8)
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
3.5
V
V
V
kΩ
pF
VIH High Level Input Voltage
VDD =1.8V
l 1.3
VIL Low Level Input Voltage
VDD =1.8V
l 0.6
IIN Input Current
VIN = 0V to 3.6V
l –10
10
CIN Input Capacitance
(Note 8)
3
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
V
V
μA
pF
ROL Logic Low Output Resistance to GND
IOH Logic High Output Leakage Current
COUT Output Capacitance
DIGITAL DATA OUTPUTS
VDD =1.8V, SDO = 0V
SDO = 0V to 3.6V
(Note 8)
l –10
200
3
10
Ω
μA
pF
VOD Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l 247 350 454
l 125 175 250
mV
mV
VOS
RTERM
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
www.DataSheet.net/
Termination Enabled, OVDD = 1.8V
l 1.125
l 1.125
1.250
1.250
100
1.375
1.375
V
V
Ω
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
VDD
OVDD
IVDD
IOVDD
PDISS
PSLEEP
PNAP
PDIFFCLK
PARAMETER
CONDITIONS
Analog Supply Voltage
(Note 10)
Output Supply Voltage
(Note 10)
Analog Supply Current
Sine Wave Input
Digital Supply Current
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
4-Lane Mode, 1.75mA Mode
4-Lane Mode, 3.5mA Mode
Power Dissipation
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
4-Lane Mode, 1.75mA Mode
4-Lane Mode, 3.5mA Mode
Sleep Mode Power
Nap Mode Power
Power Increase with Diffential Encode Mode Enabled
(No Increase for Sleep Mode)
MIN TYP MAX UNITS
l 1.7 1.8 1.9
V
l 1.7 1.8 1.9
V
l
93.3 103
mA
l
9.4 10.7
mA
l
17.5 19.6
mA
l
13.4 15.5
mA
l
25.5 29
mA
l
21.9 25
mA
l
42 47
mA
l
185 205
mW
l
199 221
mW
l
192 214
mW
l
214 238
mW
l
207 231
mW
l
244 270
mW
1 mW
50 mW
20 mW
2271f
5
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
LTC2271
PIN FUNCTIONS
VCM1 (Pin 1): Common Mode Bias Output, Nominally Equal
to VDD/2. VCM1 should be used to bias the common mode
of the analog inputs of channel 1. Bypass to ground with
a 1μF ceramic capacitor.
GND (Pins 2, 5, 13, 22, 45, 47, 49, Exposed Pad Pin 53):
ADC Power Ground. The exposed pad must be soldered
to the PCB ground.
AIN1+ (Pin 3): Channel 1 Positive Differential Analog
Input.
AIN1– (Pin 4): Channel 1 Negative Differential Analog
Input.
REFH (Pins 6, 8): ADC High Reference. See the Reference
section in the Applications Information for recommended
bypassing circuits for REFH and REFL.
REFL (Pins 7, 9): ADC Low Reference. See the Reference
section in the Applications Information for recommended
bypassing circuits for REFH and REFL.
PAR/SER (Pin 10): Programming Mode Selection Pin.
Connect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the VDD of the part and not be driven
by a logic signal.
AIN2+ (Pin 11): Channel 2 Positive Differential Analog
Input.
AIN2– (Pin 12): Channel 2 Negative Differential Analog
Input.
VCM2 (Pin 14): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM2 should be used to bias the common
mode of the analog inputs of channel 2. Bypass to ground
with a 1μF ceramic capacitor.
VDD (Pins 15, 16, 51, 52): Analog Power Supply, 1.7V
to 1.9V. Bypass to ground with 0.1μF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
ENC+ (Pin 17): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 18): Encode Complement Input. Conversion
starts on the falling edge. Tie to GND for single-ended
encode mode.
CS (Pin 19): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = VDD), CS along with SCK selects 1-,
2- or 4-lane output mode (see Table 3). CS can be driven
with 1.8V to 3.3V logic.
SCK (Pin 20): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = VDD), SCK along with CS
selects 1-, 2- or 4-lane output mode (see Table 3). SCK
can be driven with 1.8V to 3.3V logic.
SDI (Pin 21): In Serial Programming Mode, (PAR/SER =
0V), SDI is the Serial Interface Data Input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In the parallel programming pode (PAR/SER
= VDD), SDI can be used to power down the part. SDI can
be driven with 1.8V to 3.3V logic.www.DataSheet.net/
OGND (Pin 33): Output Driver Ground. This pin must be
shorted to the ground plane by a very low inductance path.
Use multiple vias close to the pin.
OVDD (Pin 34): Output Driver Supply. Bypass to ground
with a 0.1μF ceramic capacitor.
SDO (Pin 46): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control regis-
ters and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V to 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode (PAR/SER = VDD), SDO selects
3.5mA or 1.75mA LVDS output currents. When used as an
input, SDO can be driven with 1.8V to 3.3V logic through
a 1k series resistor.
VREF (Pin 48): Reference Voltage Output. Bypass to ground
with a 2.2μF ceramic capacitor. The reference output is
nominally 1.25V.
2271f
11
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC2271.PDF ] | |
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