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PDF ISL70001SEH Data sheet ( Hoja de datos )
| Número de pieza | ISL70001SEH | |
| Descripción | Rad Hard and SEE Hard 6A Synchronous Buck Regulator | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Rad Hard and SEE Hard 6A Synchronous Buck Regulator
ISL70001SEH
The ISL70001SEH is a radiation hardened and SEE hardened
high efficiency monolithic synchronous buck regulator with
integrated MOSFETs. This single chip power solution operates
over an input voltage range of 3V to 5.5V and provides a tightly
regulated output voltage that is externally adjustable from 0.8V
to ~85% of the input voltage. Output load current capacity is 6A
for TJ < +145°C.
High integration and class leading radiation tolerance makes
the ISL70001SEH an ideal choice to power many of today’s
small form factor applications. Two devices can be
synchronized to provide a complete power solution for large
scale digital ICs, like field programmable gate arrays (FPGAs),
that require separate core and I/O voltages.
Applications
• FPGA, CPLD, DSP, CPU Core or I/O Voltages
• Low-Voltage, High-Density Distributed Power Systems
Related Literature
• ISL70001SRHEVAL1Z Evaluation Board, AN1518
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed in the Ordering Information table on page 2 must
be used when ordering.
Detailed Electrical Specifications for these devices are contained
in SMD 5962-09225. This link is also available on the
ISL70001SEH device information page on the Intersil web site.
Features
• ±1% Reference Voltage Over Line, Load, Temperature and
Radiation
• Current Mode Control for Excellent Dynamic Response
• Full Mil-Temp Range Operation (TA = -55°C to +125°C)
• High Efficiency > 90%
• Fixed 1MHz Operating Frequency
• Operates from 3V to 5.5V Supply
• Adjustable Output Voltage
- Two External Resistors Set VOUT from 0.8V to ~85% of VIN
• Bi-directional SYNC Pin Allows Two Devices to be Synchronized
180° Out-of-Phase
• Device Enable with Comparator Type Input
• Power-Good Output Voltage Monitor
• Adjustable Analog Soft-Start
• Input Undervoltage, Output Undervoltage and Output
Overcurrent Protection
• Starts Into Pre-Biased Load
• Electrically Screened to DLA SMD 5962-09225
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardness
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- Total Dose [50-300rad(Si)/s] . . . . . . . . . . .100krad(Si) min
- Total Dose [<10mrad(Si)/s] . . . . . . . . . . . . .50krad(Si) min
• SEE Hardness
- SEL and SEB LETeff . . . . . . . . . . . . 86.4MeV/mg/cm2 min
- SEFI X-section (LETeff = 86.4MeV/mg/cm2) 1.4 x 10-6 cm2
max
- SET LETeff (< 1 Pulse Perturbation) 86.4MeV/mg/cm2 min
5V SUPPLY
ISL70001SEH
SYNCH
RAD HARD LDO
ISL70001SEH
CORE
AUX
RAD TOLERANT
FPGA
I/O
FIGURE 1. TYPICAL APPLICATION
95
90
85
80
75
70
0123456
LOAD CURRENT (A)
FIGURE 2. EFFICIENCY 5V INPUT TO 3.3V OUTPUT, TA = +25°C
November 30, 2011
FN7956.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
ISL70001SEH
Typical Application Schematic
PVIN1
5V
PVIN2
100µF
1µF
PVIN3
PVIN4
PVIN5
1µF
PVIN6
1 AVDD
1
VSENSE
1µF
1µF
AGND
DVDD
DGND
EN
10nF
M/S
PORSEL
TDI
TDO
ZAP
ISL70001SEH
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LX1
LX2
LX3
LX4
LX5
1µH
LX6
20V
3A
FB
0V TO 5.5V
470µF
1kΩ
1.8V
6A
499Ω
PGOOD
10nF
SYNC
REF
220nF
SS
100nF
FIGURE 3. 5V INPUT SUPPLY VOLTAGE WITH MASTER MODE SYNCHRONIZATION
5 FN7956.0
November 30, 2011
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
ISL70001SEH
The soft-start capacitor is charged by an internal ISS current
source. As the soft-start capacitor is charged, the output voltage
slowly ramps to the set point determined by the reference
voltage and the feedback network. Once the voltage on the SS
pin is equal to the internal reference voltage, the soft-start
interval is complete. The controlled ramp of the output voltage
reduces the inrush current during start-up. The soft-start output
ramp interval is defined in Equation 6 and is adjustable from
approximately 2ms to 200ms. The value of the soft-start
capacitor, CSS, should range from 8.2nF to 8.2µF, inclusive. The
peak inrush current can be computed from Equation 7. The soft-
start interval should be long enough to ensure that the peak
inrush current plus the peak output load current does not exceed
the overcurrent trip level of the regulator.
tSS = CSS ⋅ V---I-R-S---ES---F-
(EQ. 6)
IINRUSH = COUT ⋅ V---t-O-S---US---T-
(EQ. 7)
The soft-start capacitor is immediately discharged by a 2.2Ω
resistor whenever POR conditions are not met or EN is pulled low.
The soft-start discharge time is equal to 256 clock cycles.
Power-Good
The power-good (PGOOD) pin is an open-drain logic output that
indicates when the output voltage of the regulator is within
regulation limits. The power-good pin pulls low during shutdown
and remains low when the controller is enabled. After a
successful soft-start, the PGOOD pin releases, and the voltage
rises with an external pull-up resistor. The power-good signal
transitions low immediately when the EN pin is pulled low.
The power-good circuitry monitors the FB pin and compares it to
the rising and falling thresholds shown in the “Electrical
Specifications” table on page 8. If the feedback voltage exceeds
the typical rising limit of 111% of the reference voltage, the
PGOOD pin pulls low. The PGOOD pin continues to pull low until
the feedback voltage falls to a typical of 107.5% of the reference
voltage. If the feedback voltage drops below a typical of 89% of
the reference voltage, the PGOOD pin pulls low. The PGOOD pin
continues to pull low until the feedback voltage rises to a typical
92.5% of the reference voltage. The PGOOD pin then releases
and signals the return of the output voltage to within the
power-good window.
The PGOOD pin can be pulled up to any voltage from 0V to 5.5V,
independently from the supply voltage. The pull-up resistor
should have a nominal value from 1kΩ to 10kΩ. The PGOOD pin
should be bypassed to DGND, with a 10nF ceramic capacitor to
mitigate SEE.
Fault Monitoring and Protection
The ISL70001SEH actively monitors output voltage and current
to detect fault conditions. Fault conditions trigger protective
measures to prevent damage to the regulator and external load
device.
Undervoltage Protection
A hysteretic comparator monitors the FB pin of the regulator. The
feedback voltage is compared to an undervoltage threshold that
is a fixed percentage of the reference voltage. Once the
comparator trips, indicating a valid undervoltage condition, a
3-bit undervoltage counter increments. The counter is reset if the
feedback voltage rises back above the undervoltage threshold,
plus a specified amount of hysteresis outlined in the “Electrical
Specifications” table on page 8. If the 3-bit counter overflows, the
undervoltage protection logic shuts down the regulator.
After the regulator shuts down, it enters a delay interval
equivalent to the soft-start interval, which allows the device to
cool. The undervoltage counter is reset when the device enters
the delay interval. The protection logic initiates a normal
soft-start once the delay interval ends. If the output successfully
soft-starts, the power-good signal goes high, and normal
operation continues. If undervoltage conditions continue to exist
during the soft-start interval, the undervoltage counter must
overflow before the regulator shuts down again. This hiccup
mode continues indefinitely until the output soft-starts
successfully.
Overcurrent Protection
A pilot device integrated into the PMOS transistor of Power Block 4
samples current each cycle. This current feedback is scaled and
compared to an overcurrent threshold based on the number of
power blocks connected. Each additional power block connected
beyond Power Block 4 increases the overcurrent limit by 2A. For
example, if three power blocks are connected, the typical current
limit threshold would be 3 x 2A = 6A.
If the sampled current exceeds the overcurrent threshold, a 3-bit
overcurrent counter increments by one LSB. If the sampled current
falls below the threshold before the counter overflows, the counter
is reset. Once the overcurrent counter reaches 111, the regulator
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shuts down.
After the regulator shuts down, it enters a delay interval,
equivalent to the soft-start interval, which allows the device to
cool. The overcurrent counter is reset when the device enters the
delay interval. The protection logic initiates a normal soft-start
once the delay interval ends. If the output successfully
soft-starts, the power-good signal goes high, and normal
operation continues. If overcurrent conditions continue to exist
during the soft-start interval, the overcurrent counter must
overflow before the regulator shut downs the output again. This
hiccup mode continues indefinitely until the output soft-starts
successfully.
Note: To prevent severe negative ringing that can disturb the
overcurrent counter, it is recommended that a Schottky diode of
appropriate rating be added from the LXx pins to the PGNDx pins.
Feedback Loop Compensation
To reduce the number of external components and to simplify the
process of determining compensation components, the
ISL70001SEH PWM controller has an internally compensated
error amplifier.
Due to the current loop feedback in peak current mode control, the
modulator has a single pole response with -20dB slope at a
frequency determined by the load (Equation 8):
FPO = -2---π-----⋅---R----O-1----⋅---C----O----U---T-
(EQ. 8)
11
FN7956.0
November 30, 2011
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ISL70001SEH.PDF ] | |
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