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PDF PIC18F24K50 Data sheet ( Hoja de datos )
| Número de pieza | PIC18F24K50 | |
| Descripción | (PIC18F24K50 - PIC18F45K50) High-Performance Microcontrollers | |
| Fabricantes | Microchip Technology | |
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PIC18(L)F2X/45K50
28/40/44-Pin, Low-Power, High-Performance
Microcontrollers with XLP Technology
Universal Serial Bus Features:
• USB V2.0 Compliant
• Crystal-less Full Speed (12 Mb/s) and Low-Speed
Operation (1.5 Mb/s)
• Supports Control, Interrupt, Isochronous and Bulk
Transfers
• Supports up to 32 Endpoints (16 Bidirectional)
• 1 Kbyte Dual Access RAM for USB
• On-Chip USB Transceiver
Flexible Oscillator Structure:
• 3x and 4xPLL Clock Multipliers
• Two External Clock modes, Up to 48 MHz (12
MIPS)
• Internal 31 kHz Oscillator
• Internal Oscillator, 31 kHz to 16 MHz
- Factory calibrated to ± 1%
- Self-tune to ± 0.20% max. from USB or
secondary oscillator
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if any clock stops
Peripheral Highlights:
• Up to 33 I/O pins plus 3 Input-Only Pins:
- High-current Sink/Source 25 mA/25 mA
- Three programmable external interrupts
- 11 programmable interrupts-on-change
- 9 programmable weak pull-ups
- Programmable slew rate
• SR Latch
• Enhanced Capture/Compare/PWM (ECCP)
module:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
- Pulse steering control
• Capture/Compare/PWM (CCP) module
• Master Synchronous Serial Port (MSSP) module
Supporting 3-Wire SPI (all 4 modes) and I2C™
Master and Slave modes
• Two Analog Comparators with Input Multiplexing
• 10-Bit Analog-to-Digital (A/D) Converter module:
- Up to 25 input channels
- Auto-acquisition capability
- Conversion available during Sleep
• Digital-to-Analog Converter (DAC) module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
- 5-bit rail-to-rail resistive DAC with positive
and negative reference selection
• High/Low-Voltage Detect module
• Charge Time Measurement Unit (CTMU):
- Supports capacitive touch sensing for touch
screens and capacitive switches
• Enhanced USART module:
- Supports RS-485, RS-232 and LIN/J2602
- Auto-wake-up on Start bit
- Auto-Baud Detect
Extreme Low-Power Management with
XLP:
• Sleep mode: 20 nA, typical
• Watchdog Timer: 300 nA, typical
• Timer1 Oscillator: 800 nA @ 32 kHz
• Peripheral Module Disable
Special Microcontroller Features:
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• Low-Power, High-Speed CMOS Flash Technology
• C Compiler Optimized Architecture for Re-Entrant
Code
• Power Management Features:
- Run: CPU on, peripherals on, SRAM on
- Idle: CPU off, peripherals on, SRAM on
- Sleep: CPU off, peripherals off, SRAM on
• Priority Levels for Interrupts
• Self-Programmable under Software Control
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™
(ICSP™) via Two Pins
• In-Circuit Debug (ICD) with Three Breakpoints via
Two Pins
• Optional dedicated ICD/ICSP Port (44-pin TQFP
Package Only)
• Wide Operating Voltage Range:
- F devices: 2.3V to 5.5V
- LF devices: 1.8V to 3.6V
• Flash Program Memory of 10,000 Erase/Write
Cycles Minimum and 20-year Data Retention
2012 Microchip Technology Inc.
DS30684A-page 1
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
TABLE 1: PIC18(L)F2X/45K50 PIN SUMMARY
RA0
RA1
RA2
2 27
3 28
41
2 17
3 18
4 19
19
20
21
RA3 5 2
RA4 6 3
RA5 7 4
RA6 10 7
5 20
6 21
7 22
14 29
22
23
24
31
AN0
AN1
AN2
AN3
AN4
C12IN0-
C12IN1-
C2IN+
CTCMP
C1IN+
C1OUT
C2OUT
SRQ
SRNQ
VREF-
DACOUT
VREF+
HLVDIN
RA7 9 6 13 28 30
RB0 21 18 33 8 8 AN12
SRI
FLT0
RB1 22 19 34 9 9 AN10 C12IN3-
P1C(5)
RB2 23 20 35 10
RB3 24 21 36 11
RB4 25 22 37 12
RB5 26 23 38 13
10
11
14
15
AN8
AN9
AN11
AN13
CTED1
C12IN2- CTED2
P1B(5)
CCP2(1)
P1D(5)
RB6 27 24 39 14 16
RB7 28 25 40 15 17
Note 1:
2:
3:
4:
5:
6:
7:
Alternate CCP2 pin location based on Configuration bit.
Alternate T3CKI pin location based on Configuration bits.
Pins are enabled when ICPRT = 1, otherwise, they are disabled.
Location on 40/44-Pin parts (PIC18(L)F45K50). Function not on this pin on 28-Pin parts (PIC18(L)F2XK50).
Location on 28-Pin parts (PIC18(L)F2XK50). Function not on this pin on 40/44-Pin parts (PIC18(L)F45K50).
Alternate SDO pin location based on Configuration bits.
RE3 can be used for digital input only (no output functionality).
T0CKI
SS
SDI
SDA
SCK
SCL
SDO
INT0
INT1
INT2
IOCB4
T1G IOCB5
T3CKI(2)
IOCB6
IOCB7
Y
Y
Y
Y
Y
Y
Y
Y
OSC2
CLKO
OSC1
CLKI
PGC
PGD
5 Page 
PIC18(L)F2X/45K50
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC18(L)F45K50
• PIC18(L)F25K50
• PIC18(L)F24K50
This family offers the advantages of all PIC18
microcontrollers – namely, high computational
performance at an economical price – with the addition
of high-endurance, Flash program memory. On top of
these features, the PIC18(L)F2X/45K50 family
introduces design enhancements that make these
microcontrollers a logical choice for many high-
performance, power sensitive applications.
1.1 New Core Features
1.1.1 XLP TECHNOLOGY
All of the devices in the PIC18(L)F2X/45K50 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• Peripheral Module Disable bits: User code can
power down individual peripheral modules during
Run and Idle modes for further lowering dynamic
power reduction.
• On-the-fly Mode Switching: The power-
managed modes are invoked by user code during
operation, allowing the user to incorporate power-
saving ideas into their application’s software
design.
• Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See
Section 29.0 “Electrical Characteristics”
for values.
1.1.2 UNIVERSAL SERIAL BUS (USB)
Devices in the PIC18(L)F2X/45K50 family incorporate
a fully-featured USB communications module with a
built-in transceiver that is compliant with the USB
Specification Revision 2.0. The module supports both
low-speed and full-speed communication for all
supported data transfer types. The device
incorporates its own on-chip transceiver and 3.3V
regulator for USB.
1.1.3
MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18(L)F2X/45K50 family
offer ten different oscillator options, allowing users a
wide range of choices in developing application
hardware. These include:
• Four Crystal modes, using crystals or ceramic
resonators
• Six External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O)
• Two External RC Oscillator modes with the same
pin options as the External Clock modes
• An internal oscillator block which contains a
16 MHz HFINTOSC oscillator and a 31 kHz
INTRC oscillator, which together provide eight
user selectable clock frequencies, from 31 kHz to
16 MHz. This option frees the two oscillator pins
for use as additional general purpose I/O.
• 3x and 4x Phase Lock Loop (PLL) frequency
multipliers, available to both external and internal
oscillator modes, which allows clock speeds of up
to 48 MHz. Used with the internal oscillator, the
PLL gives users a complete selection of clock
speeds, from 31 kHz to 48 MHz – all without using
an external crystal or clock circuit.
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
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gives the family additional features for robust
operation:
• Active Clock Tuning: This option allows the
internal oscillator to automatically tune itself to
match USB host or external 32.768 kHz
secondary oscillator clock sources. Full-speed
USB operation can now meet specification
requirements without an external crystal, enabling
lower-cost designs.
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a
reference signal provided by the INTRC. If a clock
failure occurs, the controller is switched to the
internal oscillator block, allowing for continued
operation or a safe application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
2012 Microchip Technology Inc.
DS30684A-page 11
Datasheet pdf - http://www.Data
11 Page | ||
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