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PDF NCN49597 Data sheet ( Hoja de datos )
| Número de pieza | NCN49597 | |
| Descripción | Power Line Carrier Modem | |
| Fabricantes | ON Semiconductor | |
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NCN49597
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Power Line Carrier Modem
ON Semiconductor’s NCN49597 is an IEC 61334−5−1 compliant
power line carrier modem using spread−FSK (S−FSK) modulation for
robust low data rate communication over power lines. NCN49597 is
built around an ARM processor core, and includes the MAC layer.
With this robust modulation technique, signals on the power lines can
pass long distances. The half−duplex operation is automatically
synchronized to the mains, and can be up to 4800 bits/sec.
The product configuration is done via its serial interface, which
allows the user to concentrate on the development of the application.
The NCN49597 is implemented in ON Semiconductor mixed signal
technology, combining both analog circuitry and digital functionality
on the same IC.
Features
• Power Line Carrier Modem for 50 and 60 Hz Mains
• Fully compliant to IEC 61334−5−1 and CENELEC EN 50065−1
• Complete Handling of Protocol Layers Physical to MAC
• Programmable Carrier Frequencies in CENELEC A-Band from 9 to
95 kHz; B−Band from 95 to 125 kHz, in 10 Hz Steps
• Half Duplex
• Data Rate Selectable:
300 – 600 – 1200 − 2400 – 4800 baud (@ 50 Hz)
360 – 720 – 1440 − 2880 – 5760 baud (@ 60 Hz)www.DataSheet.net/
• Synchronization on Mains
• Repetition Algorithm Boost the Robustness of Communication
• SCI Port to Application Microcontroller
• SCI Baudrate Selectable: 9.6 – 19.2 – 38.4 − 115.2 kb
• Power Supply 3.3 V
• Ambient Temperature Range: −40°C to +80°C
• These Devices are Pb−Free and are RoHS Compliant*
Typical Applications
• ARM: Automated Remote Meter Reading
• Remote Security Control
• Streetlight Control
• Transmission of Alerts (Fire, Gas Leak, Water Leak)
http://onsemi.com
1 52
QFN52 8x8, 0.5P
CASE 485M
MARKING DIAGRAMS
52
1 ON ARM
XXXXYZZ
NCN 49597
C597−901 e3
XXXX
Y
ZZ
= Date Code
= Plant Identifier
= Traceability Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 27 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2011
December, 2011 − Rev. P0
1
Publication Order Number:
NCN49597/D
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
NCN49597
Table 4. NCN49597QFN PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
I/O Type
16
TXD/PRES
Out D, 5V Safe
17 XIN In A
18
XOUT
Out A
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
42
43
46
47
48
49
51
2, 38..41, 44,
45,50, 52
VDD1V8
VSS
VDD
TXD
RXD
SCK
SDI
SDO
CSB
T_REQ
SEN
BR1
BR0
CRC
RESB
TEST
TX_ENB
TX_OUT
ALC_IN
VDDA
VSSA
RX_OUT
RX_IN
REF_OUT
NC
P
P
P
Out D, 5V Safe
In D, 5V Safe
Out D
In D
Out D
In D
In D, 5V Safe
In D
In D, 5V Safe
In D, 5V Safe
Out D, 5V Safe
In D, 5V Safe
In D
Out
Out
D, 5V Safe
A
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In A
P
P
Out A
In A
Out A
Description
Output of transmitted data (TXD) or PRE_SLOT signal
(PRES)
Xtal input (can be driven by an internal clock)
Xtal output (output floating when XIN driven by external
clock)
1V8 regulator output. Foresee a decoupling capacitor
Digital ground
3.3V digital supply
SCI transmit output (open drain)
SCI receive input (Schmitt trigger output)
SPI interface external Flash
SPI interface external Flash
SPI interface external Flash
SPI interface external Flash
Transmit Request input
Boot option
SCI baud rate selection
SCI baud rate selection
Correct frame CRC indication (open drain output)
Master reset bar (Schmitt trigger input, active low)
Hardware Test enable (internal pull down)
TX enable bar (open drain)
Transmitter output
Automatic level control input
3.3V analog supply
Analog ground
Output of receiver low noise operational amplifier
Positive input of receiver low noise operational amplifier
Reference output for stabilization
Pins 2, 38..41, 44, 45, 50, 52 are not connected. These
pins need to be left open or connected to the GND plane.
P: Power pin
A: Analog pin
D: Digital pin
Detailed Pin Description
VDDA
VDDA is the positive analog supply pin. Nominal voltage
is 3.3 V. A ceramic decoupling capacitor CDA = 100 nF must
be placed between this pin and the VSSA. Connection path
of this capacitance to the VSSA on the PCB should be kept
as short as possible in order to minimize the serial resistance.
5V Safe:
Out:
In:
IO that support the presence of 5V on bus line
Output signal
Input signal
REF_OUT
REF_OUT is the analog output pin which provides the
voltage reference used by the A/D converter. This pin must
be decoupled to the analog ground by a 1 mF ceramic
capacitance CDREF. The connection path of this capacitor to
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5
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
NCN49597
Receiver External Parameters: Pin RX_IN, RX_OUT, REF_OUT
Table 9. RECEIVER EXTERNAL PARAMETERS
Parameter
Test Conditions
Symbol
Min
Typ
Max Unit
Input offset voltage 42 dB
Input offset voltage 0 dB
Max. peak input voltage (corres-
ponding to 62.5% of the SD full
scale)
AGC gain = 42 dB
AGC gain = 0 dB
AGC gain = 0 dB (Note 9)
VOFFS_RX_IN
VOFFS_RX_IN
VMAX_RX_IN
0.85
5 mV
50 mV
1.15 Vp
Input referred noise of the analog
receiver path
AGC gain = 42 dB
(Notes 9 and 10)
NFRX_IN
150 nV/ǠHz
Input leakage current of receiver
input
ILE_RX_IN
−1
1 mA
Max. current delivered by
REF_OUT
IMax_REF_OUT
−300
300 mA
Power supply rejection ratio of the
receiver input section
AGC gain = 42 dB (Note 11)
AGC gain = 42 dB (Note 12)
PSRRLPF_OUT
10
35
dB
AGC gain step
AGC range
Analog ground reference output
voltage
AGCstep
AGCrange
VREF_OUT
5.7
39.9
1.52
6.3 dB
44.1 dB
1.78 V
Signal to noise ratio at 62.5 % of
the SD full scale
(Notes 9 and 13)
SNAD_OUT
54
dB
Clipping level at the output of the
gain stage (RX_OUT)
VCLIP_AGC_IN
1.15
1.65 Vp
9. Input at RX_IN, no other external components.
10. Characterization data only. Not tested in production.
11. A sinusoidal signal of 10 kHz and 100 mVpp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT and
www.DataSheet.net/
REF_OUT output is measured to determine the parameter.
12. A sinusoidal signal of 50 Hz and 100 mVpp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT output is
measured to determine the parameter.
13. These parameters will be tested in production with an input signal of 95 kHz and 1 Vp by reading out the digital samples at the point AD_OUT
with the default settings of T_RX_MOD[7], SDMOD_TYP, DEC_TYP, and COR_F_ENA. The AGC gain is switched to 0 dB.
The receive LPF filter + AGC + low noise amplifier must have a frequency characteristic between the limits listed below.
The absolute output level depends on the operating condition.
Table 10. RECEIVER FREQUENCY CHARACTERISTICS
Frequency (kHz)
10
95
130
165
330
660
1000
2000
Attenuation
Min Max
−0.5 0.5
−1.3 0.5
−4.5 −2.0
−3.0
−18.0
−36.0
−50
−55
Unit
dB
dB
dB
dB
dB
dB
dB
dB
http://onsemi.com
11
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet NCN49597.PDF ] | |
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