PDF CY28RS480 Data sheet ( Hoja de datos )

Número de pieza	CY28RS480
Descripción	Clock Generator
Fabricantes	SpectraLinear
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CY28RS480 Clock Generator for ATI£ RS480 Chipset Features • Supports AMD£ CPU • 200 MHz differential CPU clock pairs • 100 MHz differential SRC clocks • 48 MHz USB clock • 33 MHz PCI clock • 66 MHz HyperTransport¥ clock Block Diagram XIN XOUT CPU_STP# CLKREQ[0:1]# XTAL OSC PLL Ref Freq PLL1 Divider Network IREF PD PLL2 SDATA SCLK I2C Logic • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 56-pin SSOP and TSSOP packages CPU x2 SRC x8 HTT66 x1 PCI x1 REF USB_48 x3 x1 Pin Configuration VDD_REF REF[0:2] VDD_CPU CPUT[0:1], CPUC[0:1], VDD_SRC SRCT[0:5],SRCC[0:5] VDD_SRCS SRCST[0:1],SRCSC[0:1] VDD_PCI PCI VDD_HTT HTT66 www.DataSheet.co.kr VDD_48 MHz USB_48 XIN XOUT VDD_48 USB_48 VSS_48 NC SCLK SDATA NC CLKREQ#0 CLKREQ#1 SRCT5 SRCC5 VDD_SRC VSS_SRC SRCT4 SRCC4 SRCT3 SRCC3 VSS_SRC VDD_SRC SRCT2 SRCC2 SRCT1 SRCC1 VSS_SRC SRCST1 SRCSC1 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 56 SSOP/TSSOP VDD_REF VSS_REF REF0 REF1 REF2 VDD_PCI PCI0 VSS_PCI VDD_HTT HTT66 VSS_HTT CPUT0 CPUC0 VDD_CPU VSS_CPU CPUT1 CPUC1 VDDA VSSA IREF VSS_SRC1 VDD_SRC1 SRCT0 SRCC0 VDD_SRCS VSS_SRCS SRCST0 SRCSC0 Rev 1.0, November 22, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 14 www.SpectraLinear.com Datasheet pdf - http://www.DataSheet4U.net/ 1 page Byte 2: Control Register 2 Bit @Pup 71 61 51 40 31 20 11 01 Byte 3: Control Register 3 Bit @Pup 71 Name CPUT/C SRCT/C USB_48 PCI Reserved Reserved CPU SRC Reserved Reserved Name CLKREQ# 60 51 40 31 21 11 01 Byte 4: Control Register 4 Bit @Pup 70 CPU SRC Reserved Reserved Reserved Reserved HTT66 Name SRC[T/C]5 60 SRC[T/C]4 50 SRC[T/C]3 40 SRC[T/C]2 30 SRC[T/C]1 20 SRC[T/C]0 11 HTT66 CY28RS480 Description Spread Spectrum Selection ‘0’ = –0.35% ‘1’ = –0.50% 48-MHz Output Drive Strength 0 = 2x, 1 = 1x 33-MHz Output Drive Strength 0 = 2x, 1 = 1x Reserved Reserved CPU/SRC Spread Spectrum Enable 0 = Spread off, 1 = Spread on Reserved Reserved Description CLKREQ# drive mode 0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when stopped CPU pd drive mode 0 = CPU clocks driven when power-down, 1 = CPU clocks tri-state SRC pd drive mode 0 = SRC clocks driven when power-down, 1 = SRC clocks tri-state Reserved Reserved Reserved www.DataSheet.co.kr Reserved HTT66 Output Drive Strength0 = High drive, 1 = Low drive. Description SRC[T/C]5 CLKREQ0 control 1 = SRC[T/C]5 stoppable by CLKREQ#0 pin 0 = SRC[T/C]5 free running SRC[T/C]4 CLKREQ#0 control 1 = SRC[T/C]4 stoppable by CLKREQ#0 pin 0 = SRC[T/C]4 free running SRC[T/C]3 CLKREQ#0 control 1 = SRC[T/C]3 stoppable by CLKREQ#0 pin 0 = SRC[T/C]3 free running SRC[T/C]2 CLKREQ#0 control 1 = SRC[T/C]2 stoppable by CLKREQ#0 pin 0 = SRC[T/C]2 free running SRC[T/C]1 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running SRC[T/C]0 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running HTT66 Output enable 0 = Disabled, 1 = Enabled Rev 1.0, November 22, 2006 Page 5 of 14 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page CY28RS480 AC Electrical Specifications (continued) Parameter Description TDC Duty Cycle TR/TF Slew Rate TCCJ Cycle to Cycle jitter TSKEW HTT66 clock to PCI clock Skew PCI TDC PCI Duty Cycle TPERIOD Spread Disabled PCI Period TPERIODSS Spread Enabled PCI Period, SSC TPERIODAbs Spread Disabled PCI Period TPERIODSSAbs Spread Enabled PCI Period, SSC THIGH PCI high time TLOW PCI low time TR / TF PCI rise and fall times TCCJ PCI Cycle to Cycle Jitter USB TDC Duty Cycle TPERIOD Period TPERIODAbs Absolute Period THIGH USB high time TLOW USB low time TR / TF Rise and Fall Times TCCJ Cycle to Cycle Jitter TLTJ Long Term Jitter REF TDC REF Duty Cycle TPERIOD REF Period TPERIODAbs REF Absolute Period TR / TF REF Rise and Fall Times TCCJ REF Cycle to Cycle Jitter ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up TSS Stopclock Set-up Time TSH Stopclock Hold Time Condition Measured at 1.5V Measured at 20% and 60% Measured at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V www.DataSheet.co.kr Measurement at 1.5V@1 us Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Min. 45 0.9 – – Max. 55 6.5 450 500 Unit % V/ns ps ps 45 29.99100 29.9910 29.49100 29.49100 12.0 12.0 1.0 – 55 % 30.00900 ns 30.15980 ns 30.50900 ns 30.65980 ns – ns – ns 4.0 V/ns 500 ps 45 55 % 20.83125 20.83542 ns 20.48125 21.18542 ns 8.094 10.036 ns 7.694 9.836 ns 1.0 2.0 V/ns – 350 ps – TBD ps 45 69.8203 68.82033 1.0 – 55 % 69.8622 ns 70.86224 ns 4.0 V/ns 1000 ps – 1.8 ms 10.0 – ns 0 – ns Rev 1.0, November 22, 2006 Page 11 of 14 Datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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