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PDF ISL98002 Data sheet ( Hoja de datos )
| Número de pieza | ISL98002 | |
| Descripción | Triple Video Digitizer | |
| Fabricantes | Intersil | |
| Logotipo |  |
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®
Data Sheet
March 26, 2008
ISL98002
FN6535.0
Triple Video Digitizer with Digital PLL
The ISL98002 3-Channel, 8-bit Analog Front End (AFE)
contains all the functions necessary to digitize analog YPbPr
video signals and RGB graphics signals from DVD players,
digital VCRs, video set-top boxes, and personal computers.
This product family’s conversion rates support HDTV
resolutions up to 1080p and PC monitor resolutions up to
UXGA, while the front end's programmable input bandwidth
ensures sharp, clear images at all resolutions.
To maximize performance with the widest variety of video
sources, the ISL98002 features a fast-responding digital PLL
(DPLL), providing extremely low jitter with PC graphics signals
and quick recovery from VCR head switching with video
signals. Integrated HSYNC and SOG processing eliminate the
need for external slicers, sync separators, Schmitt triggers,
and filters.
Glitchless, automatic Macrovision®- compliance is obtained
by a digital Macrovision® detection function that detects and
automatically removes Macrovision® from the HSYNC
signal.
Ease of use is also emphasized with features such as the
elimination of PLL charge pump current/VCO range
programming and single-bit switching between RGB and
YPbPr signals. Automatic Black Level Compensation
(ABLC™) eliminates part-to-part offset variation, ensuring
perfect black level performance in every application.
Simplified Block Diagram
Features
• 140MSPS and 170MSPS maximum conversion rates
• Glitchless Macrovision®-compliant sync separator
• Extremely fast recovery from VCR head switching
• Low PLL clock jitter (250ps peak-to-peak @ 170MSPS)
• 64 interpixel sampling positions
• 0.35VP-P to 1.4VP-P video input range
• Programmable bandwidth (100MHz to 780MHz)
• RGB 4:4:4 and YUV 4:2:2 output formats
• Low power (535mW @ 170MSPS)
• Small 10mmx10mm 72 Ld QFN package
• Completely independent 8-bit gain/10-bit offset control
• Pb-free (RoHS Compliant)
Applications
• Digital TVs
• Projectors
• Multifunction Monitors
www.DataSheet.co.kr
• Digital KVM
• RGB Graphics Processing
RGB/YPBPRIN
3
VOLTAGE
CLAMP
PGA
OFFSET
DAC
ABLC™
+ 8-BIT ADC
8
RGB/YUVOUT
X3
SOGIN
HSYNCIN
VSYNCIN
SYNC PROCESSING
DIGITAL PLL
AFE CONFIGURATION AND CONTROL
HSYNCOUT
VSYNCOUT
HSOUT
PIXELCLKOUT
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
ISL98002
Electrical Specifications Specifications apply for VA = VD = VX = 3.3V, VCORE = VCOREADC = VADC = VPLL = 1.8V, pixel rate = 140MHz for
ISL98002-140, 170MHz for ISL98002-170, fXTAL = 25MHz, TA = +25°C, unless otherwise noted. (Continued)
SYMBOL
PARAMETER
COMMENT
MIN
TYP
MAX UNIT
PD Total Power Dissipation
ISL98002-140
With grayscale ramp input
525 575 mW
ISL98002-170
With grayscale ramp input
535 600 mW
Standby Mode
ADCs, PLL powered down
35 80 mW
AC TIMING CHARACTERISTICS
PLL Jitter
(Note 4)
250 450 ps p-p
Sampling Phase Steps
5.6° per step
64
Sampling Phase Tempco
±1 ps/°C
Sampling Phase
Differential Nonlinearity
Degrees out-of-phase 360°
±3 °
HSYNC Frequency Range
10 150 kHz
fXTAL
fXTALIN
tSETUP
Crystal Frequency Range
Frequency Range with External 3.3V Clock
Signal Driving XTALIN
DATA Valid Before Rising Edge of DATACLK 15pF DATACLK load, 15pF DATA load
(Note 2)
23
23
1.3
25 27 MHz
25 33.5 MHz
ns
tHOLD
DATA Valid After Rising Edge of DATACLK 15pF DATACLK load, 15pF DATA load
(Note 2)
2.0
ns
AC TIMING CHARACTERISTICS (2-WIRE INTERFACE)
fSCL
SCL Clock Frequency
Maximum Width of a Glitch on SCL That Will 2 XTAL periods min
Be Suppressed
0 400 kHz
80 ns
tAA
tBUF
SCL LOW to SDA Data Out Valid
Time the Bus Must Be Free Before a New
Transmission Can Start
5 XTAL periods plus SDA’s RC time
constant
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1.3
See
comment
µs
µs
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
NOTES:
Clock LOW Time
Clock HIGH Time
Start Condition Set-up Time
Start Condition Hold Time
Data In Set-up Time
Data In Hold Time
Stop Condition Set-up Time
Data Output Hold Time
4 XTAL periods min
1.3
0.6
0.6
0.6
100
0
0.6
160
µs
µs
µs
µs
ns
ns
µs
ns
2. Setup and hold times are specified for a 170MHz DATACLK rate.
3. Linearity tested at room temperature and guaranteed across commercial temperature range by correlation to characterization.
4. Jitter tested at rated frequencies (170MHz, 140MHz) and at minimum frequency (10MHz).
5 FN6535.0
March 26, 2008
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
Register Listing (Continued)
ADDRESS
REGISTER (DEFAULT VALUE)
0x05
Input configuration (0x00)
0x06
0x07
0x08
Red Gain (0x55)
Green Gain (0x55)
Blue Gain (0x55)
ISL98002
BIT(S) FUNCTION NAME
DESCRIPTION
0 Reserved
Set to 0.
1 Input Coupling
0: AC coupled (positive input connected to clamp
DAC during clamp time, negative input disconnected
from outside pad and always internally tied to
appropriate clamp DAC)
2 RGB/YPbPr
1: DC coupled (+ and - inputs are brought to pads and
never connected to clamp DACs). Analog clamp
signal is turned off in this mode.
0: RGB inputs
Base ABLC target code = 0x00 for R, G, and B)
1: YPbPr inputs
Base ABLC target code = 0x00 for G (Y)
Base ABLC target code = 0x80 for R (Pr) and B (Pb)
3 Sync Type
0: Separate HSYNC/VSYNC
1: Composite (from SOG or CSYNC on HSYNC)
4 Composite Sync
Source
5 COAST CLAMP
enable
0: SOGIN
1: HSYNCIN
Note: If Sync Type = 0, the multiplexer will pass
HSYNCIN regardless of the state of this bit.
0: DC restore clamping and ABLC™ suspended
during COAST
1: DC restore clamping and ABLC™ continue during
COAST
6 Sync Mask Disable 0: Interval between HSYNC pulses masked
(preventing PLL from seeing Macrovision and any
spurious glitches)
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1: Interval between HSYNC pulses not masked
(Macrovision will cause PLL to lose lock)
7 HSYNCOUT Mask
Disable
7:0 Red Gain
7:0 Green Gain
7:0 Blue Gain
0: HSYNCOUT signal is masked (any Macrovision,
sync glitches on incoming SYNC are stripped from
HSYNCOUT)
1: HSYNCOUT signal is not masked (any
Macrovision, sync glitches on incoming SYNC
appear on HSYNCOUT)
If Sync Mask Disable = 1, HSYNCOUT is not masked.
Channel gain, where:
gain (V/V) = 0.5 + [7:0]/170
0x00: gain = 0.5V/V
(1.4VP-P input = full range of ADC)
0x55: gain = 1.0V/V
(0.7VP-P input = full range of ADC)
0xFF: gain = 2.0V/V
(0.35VP-P input = full range of ADC)
11
FN6535.0
March 26, 2008
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ISL98002.PDF ] | |
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