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PDF BRCA016GWZ-W Data sheet ( Hoja de datos )
| Número de pieza | BRCA016GWZ-W | |
| Descripción | WLCSP EEPROM | |
| Fabricantes | ROHM Semiconductor | |
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Datasheet
Serial EEPROM Series Standard EEPROM
WLCSP EEPROM
BRCA016GWZ-W (16Kbit)
General Description
BRCA016GWZ-W series is a serial EEPROM of I2C BUS Interface Method.
Features
■ Completely conforming to the world standard I2C BUS. All controls available by 2 ports of serial clock (SCL)
and serial data (SDA)
■ Other devices than EEPROM can be connected to the same port, saving microcontroller port.
■ 1.7V to 3.6V Single Power Source Operation most suitable for battery use.
■ Possible FAST MODE 400KHz operation
■ Page Write Mode useful for initial value write at factory shipment.
■ Self-timed Programming Cycle
■ Low Current Consumption
¾ At Write Operation (5V)
: 0.5mA (Typ)
¾ At Read Operation (5V)
: 0.2mA (Typ)
¾ At Standby Operation (5V) : 0.1μA (Typ)
■ Prevention of Write Mistake
¾ Write (write protect) function added
¾ Prevention of write mistake at low voltage
■ UCSP30L1 Compact Package
¾ W(Typ) x D(Typ) x H(Max) :1.30mm x 0.77mm x 0.35mm
■ More than 1 million write cycles
■ More than 40 years data retention
■ Noise Filter Built in SCL / SDA terminal
■ Initial Delivery State FFh
BRCA016GWZ-W
Capacity
Bit Format
Type
Power Source Voltage
Package
16Kbit
2K×8
Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
BRCA016GWZ-W
Limit
Unit
1.7V to 3.6V
UCSP30L1
Remark
Supply Voltage
VCC
-0.3 to +6.5
V
Permissible Dissipation
Pd
220
mW Derate by 2.2mW/°C when operating above Ta=25°C
Storage Temperature
Tstg
-65 to +125
°C
Operating Temperature
Topr
-40 to +85
°C
Input Voltage/
Output Voltage
-
-0.3 to Vcc+1.0
V
Memory Cell Characteristics (Ta=25°C, Vcc=1.7V to 3.6V)
Parameter
Limit
Min Typ Max
Write Cycles (1)
100,000 -
-
Unit
Times
Data Retention (1)
(1) Not 100% TESTED
40 - - Years
○Product structure：Silicon monolithic integrated circuit
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This product has no designed protection against radioactive rays
1/22
TSZ02201-0R2R0G100510-1-2
25.Feb.2013 Rev.002
1 page  
BRCA016GWZ-W (16Kbit)
Typical Performance Curves
Datasheet
Supply Voltage : VCC(V)
Figure 2. Input High Voltage1 vs Supply Voltage
(SCL,SDA,WP)
Supply Voltage : VCC(V)
Figure 3. Input Low Voltage1 vs Supply Voltage
(SCL,SDA,WP)
Output Low Current: IOL (mA)
Figure 4. Output Low Voltage1 vs Output Low
Current (VCC=2.5V)
Output Low Current: IOL (mA)
Figure 5. Output Low Voltage2 vs Output Low Current
(VCC=1.7V)
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/22
TSZ02201-0R2R0G100510-1-2
25.Feb.2013 Rev.002
5 Page 
BRCA016GWZ-W (16Kbit)
Datasheet
Timing Chart
1. I2C BUS Data Communication
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each byte. I2C BUS data communication with several devices is possible by
connecting with 2 communication lines: serial data (SDA) and serial clock (SCL).
Among the devices, there should be a “master” that generates clock and control communication start and end. The rest
become “slave” which are controlled by an address peculiar to each device, like this EEPROM. The device that outputs
data to the bus during data communication is called “transmitter”, and the device that receives data is called “receiver”.
SDA
1-7 8 9
1-7 8 9
1-7 8
SCL
S
START ADDRESS
condition
R/W
ACK
DATA
ACK
DATA
Figure 26. Data Transfer Timing
9
P
ACK STOP
condition
2. Start Condition (Start Bit Recognition)
(1) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL
is 'HIGH' is necessary.
(2) This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition
is satisfied, any command cannot be executed.
3. Stop Condition (Stop Bit Recognition)
(1) Each command can be ended by a stop condition (stop bit) where SDA goes from 'LOW' to 'HIGH' while SCL is
'HIGH'
4. Acknowledge (ACK) Signal
(1) The acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
a master-slave communication, the device (Ex. µ-COM sends slave address input for write or read command, to
this IC ) at the transmitter (sending) side releases the bus after output of 8bit data.
(2) The device (Ex. This IC receives the slave address input for write or read command from the µ-COM) at the
receiver (receiving) side sets SDA 'LOW' during the 9th clock cycle, and outputs acknowledge signal (ACK signal)
showing that it has received the 8bit data.
(3) This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
(4) After receiving 8bit data (word address and write data) during each write operation, this IC outputs acknowledge
signal (ACK signal) 'LOW'..
(5) During read operation, this IC outputs 8bit data (read data) and detects acknowledge signal (ACK signal) 'LOW'.
When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side,
this IC continues to output data. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer,
recognizes stop condition (stop bit), and ends read operation. Then this IC becomes ready for another
transmission.
5. Device Addressing
(1) Slave address comes after start condition from master.
(2) The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to '1010'.
(3) Next slave addresses (P2 P1 P0) are upper 3bit of word address, put these and word address ( WA0 to WA7 )
together, 11bit word address ( 2048byte ) of the device specified.
(4) The most insignificant bit ( R / W --- READ / WRITE) of slave address is used for designating write or read
operation, and is as shown below.
Setting R / W to 0 ------- write (setting 0 to word address setting of random read)
Setting R / W to 1 ------- read
Type
Slave address
BRCA016GWZ-W
1 0 1 0 P2 P1 P0 R / W
P0 to P2 are page select bits (Upper 3bit of word address).
Maximum Number of
Connected Buses
1
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
11/22
TSZ02201-0R2R0G100510-1-2
25.Feb.2013 Rev.002
11 Page | ||
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