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PDF LC89075W-H Data sheet ( Hoja de datos )

Número de pieza LC89075W-H
Descripción Digital Audio Interface Receiver
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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No Preview Available ! LC89075W-H Hoja de datos, Descripción, Manual

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Ordering number : ENA1858A
CMOS IC
LC89075W-H Digital Audio Interface Receiver
with Stereo ADC and Audio Selector
1. Overview
The LC89075W-H is a digital audio interface receiver that demodulates signals according to the data transfer format
between digital audio devices via IEC60958/61937 and JEITA CPR-1205 and supports demodulation sampling
frequencies of up to 192kHz.
The LC89075W-H also incorporates a high performance 24-bit single-end input ΔΣ stereo analog to digital converter that
supports sampling frequencies of up to 96kHz, and an audio selector that can support 8-channel data.
The LC89075W-H is a complete analog and digital front-end for use in various systems including AV receivers, digital
TVs, and DVD recorders.
2. Features
2.1 ADC
• ΔΣ stereo ADC
Built-in anti-aliasing digital filter
Single-end input (3Vp-p)
Built-in digital HPF for canceling DC offset
Built-in PGA (-4.5dB to 6dB/1.5dB step)
Built-in soft mute and attenuator (0dB to -63.5dB/0.25dB step, -)
Sampling frequency: 8kHz to 96kHz
Master clock: 512fs, 256fs (master/slave)
Audio data output interface: 24-bit I2S/left justified
Analog audio data detection (threshold level: -30dB to -60dB/adjustable in 2dB steps)
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment. The products mentioned herein
shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life,
aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system,
safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives
in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any
guarantee thereof. If you should intend to use our products for new introduction or other application different
from current conditions on the usage of automotive device, communication device, office equipment, industrial
equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the
intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely
responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
O2611HKIM 20111007-S00001/40411HKIM No.A1858-1/69
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LC89075W-H pdf
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LC89075W-H
Continued from preceding page.
No Name I/O
Function
22 MPOUT4
O 2ch audio data output pin
from ADC, [DATAIN], [MPIN4], [MPIO4], [RXIN5]
DSD data output pin
from [DATAIN], [MPIN4], [MPIO4], [RXIN5]
Input S/PDIF through output pin
23 ERRF
O PLL lock error, data error flag output pin
External error signal output pin
from [MPIN4]
24 MUTEB
O Clock switching period data mute signal output pin
External data mute signal output pin
from [MPIN5]
25 NPCMF
O Channel status data delimiter bit (bit 1) output pin
External non-PCM signal output pin
from [MPIN6]
26 MPIO1
O Channel status data delimiter bit (bit 1) output pin
Microcontroller extended register output pin
I Master clock input pin (ADC slave operation)
to ADC, [MPOUT1]
Group C
: Master clock input pin
to [MCKOUT], [MPOUT1]
3.3V tolerance TTL-compatible S/PDIF input pin
27 MPIO2
O Channel status copy bit output pin
Microcontroller extended register output pin
I Bit clock input pin (ADC slave operation)
to ADC, [MPOUT2]
Group C
: Bit clock input pin
to [BCKOUT], [MPOUT2]
3.3V tolerance TTL-compatible S/PDIF input pin
28 MPIO3
O Channel status emphasis information output pin
Microcontroller extended register output pin
I LR clock input pin (ADC slave operation)
to ADC
Group C
: LR clock input pin
to [LRCKOUT], [MPOUT3]
Group C
: DSD data input pin
to [LRCKOUT], [MPOUT3]
3.3V tolerance TTL-compatible S/PDIF input pin
29 MPIO4
O Channel status age bit output pin
Microcontroller extended register output pin
2ch audio data output pin (ADC slave operation)
from ADC
I Group C
: 2ch audio data input pin
to [DATAOUT], [MPOUT4]
Group C
: DSD data input pin
to [DATAOUT], [MPOUT4]
3.3V tolerance TTL-compatible S/PDIF input pin
30 XMCK
O Oscillation amplifier clock output pin
31 XOUT
O Crystal resonator connection output pin
32 XIN
I Crystal resonator connection or external clock input pin
(12.288MHz or 24.576MHz)
33 DGND
Digital GND
34 DVDD
35 XMODE
Digital power supply (3.3V)
I System reset input pin
(when power-on reset is used: fixed at “H”)
36 CSB
I SPI microcontroller I/F, chip enable input pin
37 SCK
I SPI microcontroller I/F, shift clock input pin
38 SI
I SPI microcontroller I/F, write data input pin
39 SO
O SPI microcontroller I/F, read data output pin
40 INTB
O SPI microcontroller I/F, interrupt signal output pin
41 DSTATE
O Analog or digital data detection flag output pin
42 DVDD
43 DGND
Digital power supply (3.3V)
Digital GND
Continued on next page.
No.A1858-5/69
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LC89075W-H arduino
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LC89075W-H
7.6 AC Characteristics 1
Table 7.6 AC Characteristics at Ta=-30 to 85°C,
AVDD=4.5 to 5.5V, PVDD=DVDD=3.0 to 3.6V, AGND=PGND=DGND=0V
Parameter
Symbol Conditions
min
RXIN1 to 8, RXIN1A to 3A
MPIO[4:1] input receive frequency
RXIN1 to 8, RXIN1A to 3A
MPIO[4:1] input duty factor
XIN clock input frequency
fRFS
tRXDUY
fXF
7.6.1
7.6.2
28
40
XIN clock input duty factor
MCKOUT clock output frequency
MCKOUT clock output duty factor
MCKOUT clock jitter
MPOUT1 clock output frequency
BCKOUT, MPOUT2 clock output frequency
LRCKOUT, MPOUT3 clock output frequency
MCKOUT-BCKOUT output delay
BCKOUT-LRCKOUT output delay
BCKOUT-DATAOUT output delay
BCKOUT-MPOUT[3:1](6ch, 8ch) output delay
fXDUY
fMCK1
fMCKDUY
Tj
fMCK2
fBCK1
fLRCK1
tMBO
tBLO
tBDO
7.6.3
7.6.4
7.6.4
7.6.5
40
4
40
2
0.5
8
-10
-10
-10
-10
LRCKOUT-DATAOUT output delay
tLDO
LRCKOUT-MPOUT[3:1](6ch, 8ch) output delay
7.6.5
7.6.1: “XINSEL[1:0]=00”
7.6.2: Other than “XINSEL[1:0]=00”
7.6.3: Period jitter value
7.6.4: This also applies to the output when DSD data is input.
7.6.5: “SW1SEL[1:0]=010 or 011”, “SW2SEL[1:0]=110 or 111”
-10
-10
typ
50
12.288
24.576
50
50
50
max
195
Unit
kHz
60
60
50
60
25
12.5
192
10
10
10
10
10
10
%
MHz
MHz
%
MHz
%
ps RMS
MHz
MHz
kHz
ns
ns
ns
ns
ns
ns
RXIN1 to 8
RXIN1A to 3A
MPIO[4:1]
MCKOUT
MPOUT1
BCKOUT
MPOUT2
LRCKOUT
MPOUT3
DATAOUT
MPOUT[3:1]
Input
Output
Output
tMBO
Output
Output
tRXDUY tRXDUY
tMBO
tBLO
tLDO
tMCKDUY
tMCKDUY
tBDO
Figure 7.1 AC Characteristics 1
No.A1858-11/69
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