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PDF HT46R75D-3 Data sheet ( Hoja de datos )
| Número de pieza | HT46R75D-3 | |
| Descripción | Dual Slope A/D Type 8-Bit OTP MCU | |
| Fabricantes | Holtek Semiconductor | |
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www.DataSheet.co.kr
HT46R75D-3
Dual Slope A/D Type 8-Bit OTP MCU with LCD
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Three system oscillators:
External Crystal oscillator -- HXT
External RC oscillator -- ERC
Internal High Frequency RC oscillator -- HIRC
· Up to 22 bidirectional I/O lines
· One external interrupt input shard with an I/O lines
· One 8-bit and two 16-bit programmable timer/event
counter with overflow interrupt and an 8-bit prescaler
· LCD driver with 24´8 or 28´4 segments
· LCD bias type: 1/3 bias R type or C type
· Program Memory: 8K´16
· Data Memory: 192´8
· Single differential input channel dual slope Analog to
Digital Converter with Operational Amplifier
· Watchdog Timer with regulator power
· Buzzer output
· Internal 12kHz RC oscillator
· External 32.768kHz Crystal oscillator
· Power-down and wake-up features reduce power
consumption
· Voltage regulator (3.3V) and charge pump
· Embedded voltage reference generator (1.5V)
· 8 subroutine nesting levels
· 16-bit table read instruction
· Low Voltage Reset function
· One vibration sensor input
· Four touch-key inputs
· Bit manipulation instruction
· Up to 0.5ms instruction cycle with 8MHz system clock
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
· 64-pin LQFP package
General Description
The HT46R75D-3 is an 8-bit high performance, RISC
architecture microcontroller device specifically de-
signed for A/D with LCD applications that interface di-
rectly to analog signals, such as those from sensors.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, Dual slope A/D
converter, LCD display, HALT and wake-up functions,
watchdog timer, as well as low cost, enhance the versa-
tility of these devices to suit for a wide range of AD with
LCD application possibilities such as sensor signal pro-
cessing, scales, consumer products, subsystem con-
trollers, etc.
Rev. 1.00
1 July 19, 2011
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
HT46R75D-3
Pin Name
DSRR
DSRC
DSCC
VDD
VSS
AVDD
AVSS
I/O
AI/AO
PWR
PWR
PWR
PWR
Options
¾
¾
¾
¾
¾
Description
Dual slope A/D converter main function RC circuit. DSRR is the input or
reference signal, DSRC is the Integrator negative input, and DSCC is the
comparator negative input.
Digital positive power supply
Digital Negative Power supply, ground
Analog positive power supply
Analog negative power supply, ground
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-20°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
VDD Operating Voltage
Test Conditions
VDD Conditions
¾ fSYS=4MHz
¾ fSYS=8MHz
Min.
2.2
3.3
IDD1
Operating Current (Crystal OSC,
Ext. RC OSC, Int. RC OSC)
5V
No load, fSYS=8MHz,
analog block off
¾
IDD2
Operating Current (Crystal OSC, 3V No load, fSYS=4MHz,
Ext. RC OSC, Int. RC OSC)
5V ADC block off
¾
¾
IDD3
Operating Current
(Crystal OSC, Ext. RC OSC)
3V No load, fSYS=2MHz,
5V ADC block off
¾
¾
IDD4
Operating Current
(Crystal OSC, Ext. RC OSC)
VREGO=3.3V, fSYS=4MHz,
5V
ADC on, ADCCCLK=
125kHz (all other analog de-
vices off)
¾
ISTB1
Standby Current
(WDT Disable)
3V No load, system HALT,
5V LCD off at HALT
¾
¾
ISTB2
Standby Current
(WDT Enable)
3V No load, system HALT,
5V LCD off at HALT, ADC off
¾
¾
ISTB3
Standby Current (WDT Disable In- 3V No load, system HALT,
ternal RC 12kHz OSC ON)
5V LCD off at HALT, ADC off
¾
¾
ISTB4
Standby Current
(WDT Disable,
LCD On and Regulator On)
No load, system osc HALT,
internal RC 12kHz OSC
5V On, ADC block Off,
LCD ON (1/3 bias, R type)
at HALT
¾
Typ.
¾
¾
4
0.8
2.5
0.5
1.5
3
¾
¾
2.5
8
2
6
380
Ta=25°C
Max. Unit
5.5 V
5.5 V
8 mA
1.5 mA
4 mA
1 mA
3 mA
5 mA
1 mA
2 mA
5 mA
15 mA
5 mA
10 mA
500 mA
Rev. 1.00
5 July 19, 2011
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
HT46R75D-3
Stack Register - STACK
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 8 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At a
commencement of a subroutine call or an interrupt ac-
knowledgment, the content of the program counter is
pushed onto the stack. At the end of the subroutine or in-
terrupt routine, signaled by a return instruction (RET or
RETI), the contents of the program counter is restored
to its previous value from the stack. After chip reset, the
SP will point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the ac-
knowledgment is still inhibited. Once the SP is decre-
mented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the program-
mer to use the structure easily. Likewise, if the stack is
full, and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent 8 return addresses are stored).
P ro g ra m C o u n te r
T o p o f S ta c k
S ta c k
P o in te r
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k L e v e l 3
P ro g ra m
M e m o ry
B o tto m o f S ta c k
S ta c k L e v e l 8
Data Memory - RAM
The data memory is divided into two functional groups,
namely the special function registers and the general
purpose data memory of 192´8 bit capacity. Most of
them are read/write, but some are read only.
The unused space before 40H is reserved for future ex-
panded usage and reading these locations will return
the result 00H. The general purpose data memory, ad-
dressed from 40H to FFH, is used for data and control
information under instruction command. The areas in
the RAM can directly handle arithmetic, logic, incre-
ment, decrement, and rotate operations. Except some
dedicated bits, each bit in the RAM can be set and reset
by ²SET [m].i² and ²CLR [m].i². They are also indirectly
accessible through the Memory pointer register 0 (MP0;
01H) or the Memory pointer register 1 (MP1; 03H).
Bank 1 contains the LCD Data Memory locations. After
first setting up BP to the value of ²01H² to access Bank 1
this bank must then be accessed indirectly using the
Memory Pointer MP1. With BP set to a value of ²01H²,
using MP1 to indirectly read or write to the data memory
areas with addresses from 40H~5BH will result in oper-
ations to Bank 1. Directly addressing the Data Memory
will always result in Bank 0 being accessed irrespective
of the value of BP.
B ank 0
B ank 0
0 0 H IA R 0
01H M P 0
0 2 H IA R 1
03H M P 1
04H B P
05H A C C
06H P C L
07H TB LP
08H TB LH
09H C TR L0
0A H S TA TU S
0 B H IN T C 0
0C H
0D H TM R 0
0E H TM R 0C
0FH TM R 1H
10H TM R 1L
11H TM R 1C
12H P A
13H P A C
14H P B
15H P B C
16H
17H
18H A D C R
19H
1A H A D C D
1B H
1C H W D TC
1D H W D TD
1 E H IN T C 1
1FH C H P R C
20H TM R 2H
21H TM R 2L
22H TM R 2C
23H
24H
25H
26H H A LTC
27H LC D O U T
28H C TR L1
2 9 H V IB R C
2A H R E G C
2B H P C
2C H P C C
2D H P A W K
2E H P A P U
2FH P B P U
30H P C P U
31H S FS
32H
33H LC D C
3 4 H M F IC
35H
36H
37H
38H TK M 016D H
39H TK M 016D L
3A H
3B H
3C H TK M 0C 0
3D H TK M 0C 1
3E H TK M 0C 2
3FH TK M 0C 3
40H
G e n e ra l
5 B H P u rp o s e
D a ta M e m o ry
LC D R A M
(2 8 B y te s )
(1 9 2 B y te s )
7FH
: u n im p le m e n te d , r e a d a s " 0 "
RAM Mapping
S p e c ia l P u r p o s e
D a ta M e m o ry
Rev. 1.00
11 July 19, 2011
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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