PDF FM25L256 Data sheet ( Hoja de datos )

Número de pieza	FM25L256
Descripción	3V F-RAM Memory
Fabricantes	Ramtron
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No Preview Available ! www.DataSheet.co.kr Pre-Production FM25L256 256Kb FRAM Serial 3V Memory Features 256K bit Ferroelectric Nonvolatile RAM • Organized as 32,768 x 8 bits • Unlimited Read/Write Cycles • 10 Year Data Retention • NoDelay™ Writes • Advanced High-Reliability Ferroelectric Process Very Fast Serial Peripheral Interface - SPI • Up to 25 MHz Frequency • Direct Hardware Replacement for EEPROM • SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Write Protection Scheme • Hardware Protection • Software Protection Low Power Consumption • Low Voltage Operation 2.7V – 3.6V • 1 µA (typ) Standby Current Industry Standard Configurations • Industrial Temperature -40°C to +85°C • 8-pin SOIC and 8-pin DFN Packages • “Green” Packaging Options Description The FM25L256 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM25L256 performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. The next bus cycle may start immediately. In addition, the product offers virtually unlimited write endurance. Also, FRAM exhibits much lower power consumption than EEPROM. These capabilities make the FM25L256 ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25L256 provides substantial benefits to users of serial EEPROM as a hardware drop-in replacement. The FM25L256 uses the high-speed SPI bus, which enhances the high-speed write capability of FRAM technology. Device specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration CS SO WP VSS 1 2 3 4 8 VDD 7 HOLD 6 SCK 5 SI /CS 1 SO 2 /WP 3 VSS 4 8 VDD 7 /HOLD 6 SCK 5 SI Top View Pin Name /CS /WP /HOLD SCK SI SO VDD VSS Function Chip Select Write Protect Hold Serial Clock Serial Data Input Serial Data Output Supply Voltage (2.7 to 3.6V) Ground Ordering Information FM25L256-S 8-pin SOIC FM25L256-G “Green” 8-pin SOIC FM25L256-DG “Green” 8-pin DFN This is a product in the pre-production phase of development. Device characterization is complete and Ramtron does not expect to change the specifications. Ramtron will issue a Product Change Notice if any specification changes are made. Rev. 2.0 Apr. 2005 Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 www.ramtron.com Page 1 of 14 Datasheet pdf - http://www.DataSheet4U.net/ 1 page www.DataSheet.co.kr FM25L256 Power Up to First Access The FM25L256 is not accessible for a period of time (10 ms) after power up. Users must comply with the timing parameter tPU, which is the minimum time from VDD (min) to the first /CS low. Data Transfer All data transfers to and from the FM25L256 occur in 8-bit groups. They are synchronized to the clock signal (SCK), and they transfer most significant bit (MSB) first. Serial inputs are registered on the rising edge of SCK. Outputs are driven from the falling edge of SCK. Command Structure There are six commands called op-codes that can be issued by the bus master to the FM25L256. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations. They perform a single function such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate on the status register. The third group includes commands for memory transactions followed by address and one or more bytes of data. Table 1. Op-code Commands Name Description WREN Set Write Enable Latch WRDI Write Disable RDSR Read Status Register WRSR Write Status Register READ Read Memory Data WRITE Write Memory Data Op-code 0000 0110b 0000 0100b 0000 0101b 0000 0001b 0000 0011b 0000 0010b WREN - Set Write Enable Latch The FM25L256 will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the status register and writing the memory. Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the status register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the status register has no effect on the state of this bit. Completing any write operation will automatically clear the write-enable latch and prevent further writes without another WREN command. Figure 5 below illustrates the WREN command bus configuration. WRDI - Write Disable The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the status register and verifying that WEL=0. Figure 6 illustrates the WRDI command bus configuration. CS SCK SI SO 01 2 3 4 5 6 7 00 00 0 11 0 Hi-Z Figure 5. WREN Bus Configuration Rev. 2.0 Apr. 2005 Page 5 of 14 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page www.DataSheet.co.kr Serial Data Bus Timing CS SCK SI SO tCSU 1/tCK tH tSU tF tODV tR tOH FM25L256 tCL tCH tD tCSH tOD /Hold Timing CS SCK HOLD SO Power Cycle Timing tHS tHH tHS tHH tHZ tLZ Data Retention (VDD = 2.7V to 3.6V) Parameter Data Retention Min 10 Max Units - Years Notes Rev. 2.0 Apr. 2005 Page 11 of 14 Datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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