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PDF SY54011R Data sheet ( Hoja de datos )
| Número de pieza | SY54011R | |
| Descripción | Low Voltage 1.2V/1.8V CML 1:2 Fanout Buffer | |
| Fabricantes | Micrel Semiconductor | |
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SY54011R
Low Voltage 1.2V/1.8V CML 1:2 Fanout
Buffer, 3.2Gbps, 3.2GHz
General Description
The SY54011R is a fully differential, low voltage
1.2V/1.8V CML 1:2 fanout buffer. It is optimized to
provide two identical output copies with less than 15ps
of skew and less than 10pspp total jitter. The SY54011R
can process clock signals as fast as 3.2GHz or data
patterns up to 3.2Gbps.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled
from a 2.5V driver) as small as 100mV (200mVPP)
without any level-shifting or termination resistor
networks in the signal path. For AC-coupled input
interface applications, an integrated voltage reference
(VREF-AC) is provided to bias the VT pin. The outputs are
CML, with extremely fast rise/fall times guaranteed to be
less than 95ps.
The SY54011R operates from a 2.5V ±5% core supply
and a 1.8V or 1.2V ±5% output supply and is
guaranteed over the full industrial temperature range
(–40°C to +85°C). The SY54011R is part of Micrel’s
high-speed, Precision Edge® product line.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Features
Precision Edge®
∑ 1.2V/1.8V CML 1:2 fanout buffer
∑ Guaranteed AC performance over temperature and
voltage:
– DC-to- > 3.2Gbps throughput
– <300ps propagation delay (IN-to-Q)
– <15ps within-device skew
– <95ps rise/fall times
∑ Ultra-low jitter design
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter
– <1psRMS random jitter
– <10psPP deterministic jitter
∑ High-speed CML outputs
∑ 2.5V ±5% , 1.8/1.2V ±5% power supply operation
∑ Industrial temperature range: –40°C to +85°C
∑ Available in 16-pin (3mm x 3mm) MLF® package
Applications
∑ Data Distribution: OC-48, OC-48+FEC
∑ SONET clock and data distribution
∑ Fibre Channel clock and data distribution
∑ Gigabit Ethernet clock and data distribution
Markets
∑ Storage
∑ ATE
∑ Test and measurement
∑ Enterprise networking equipment
∑ High-end servers
∑ Access
∑ Metro area network equipment
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 2008
M9999-033108-A
[email protected] or (408) 955-1690
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
Micrel, Inc.
Interface Applications
For Input Interface Applications see Figures 4a-f and
for CML Output Termination see Figures 5a-d.
CML Output Termination with VCCO 1.2V
For VCCO of 1.2V, Figure 5a, terminate the output
with 50Ω-to-1.2V, DC-coupled, not 100Ω differentially
across the outputs.
If AC-coupling is used, Figure 5d, terminate into 50Ω-
to-1.2V before the coupling capacitor and then
connect to a high value resistor to a reference
voltage.
Do not AC couple with internally terminated receiver.
For example, 50Ω ANY-IN input. AC-coupling will
offset the output voltage by 200mV and this offset
voltage will be too low for proper driver operation.
Any unused output pair needs to be terminated when
VCCO is 1.2V, do not leave floating.
SY54011R
CML Output Termination with VCCO 1.8V
For VCCO of 1.8V, Figure 5a and Figure b, terminate
with either 50Ω-to-1.8V or 100Ω differentially across
the outputs. AC- or DC-coupling is fine.
Input AC Coupling
The SY54011R input can accept AC coupling from
any driver. Tie VT to VREF-AC and bypass with a
0.1µF capacitor as shown in Figures 4c and 4d.
Timing Diagrams
Figure 1a. Propagation Delay
March 2008
5 M9999-033108-A
[email protected] or (408) 955-1690
Datasheet pdf - http://www.DataSheet4U.net/
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet SY54011R.PDF ] | |
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