PDF CY25423 Data sheet ( Hoja de datos )

Número de pieza	CY25423
Descripción	(CY254x3) Three PLL Programmable Clock Generator
Fabricantes	Cypress Semiconductor
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Hay una vista previa y un enlace de descarga de CY25423 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas
No Preview Available ! CY25403/CY25423/CY25483 Three PLL Programmable Clock Generator with Spread Spectrum Features ■ Three fully integrated phase-locked loops (PLLs) ■ Input frequency range ❐ External crystal: 8 to 48 MHz ❐ External reference: 8 to 166 MHz clock ■ Reference clock input voltage range ❐ 1.8 V for CY25403/CY25423/CY25483 ■ Wide operating output frequency range ❐ 3 to 166 MHz ■ Programmable spread spectrum with center and down spread option and lexmark and linear modulation profiles ■ VDD supply voltage options: ❐ 2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483 ■ Selectable output clock voltages independent of VDD supply: ❐ 2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483 ■ Frequency select feature with option to select four different frequencies ■ Power-down, output enable, and SS ON/OFF controls ■ Low jitter, high accuracy outputs ■ Ability to synthesize nonstandard frequencies with Fractional-N capability ■ Three clock outputs with programmable drive strength ■ Glitch-free outputs while frequency switching ■ 8-pin SOIC package ■ Commercial and Industrial temperature ranges Benefits ■ Multiple high performance PLLs allow synthesis of unrelated frequencies ■ Nonvolatile programming for personalization of PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies ■ Application specific programmable EMI reduction using Spread Spectrum for clocks ■ Programmable PLLs for system frequency margin tests ■ Meets critical timing requirements in complex system designs ■ Suitability for PC, consumer, portable, and networking applications ■ Capable of Zero PPM frequency synthesis error ■ Uninterrupted system operation during clock frequency switch ■ Application compatibility in standard and low power systems Block Diagram XIN/ EXCLKIN XOUT OSC FS0 FS1 SSON PD#/OE MUX and Control Logic PLL1 PLL 2 (SS) PLL3 (SS) Crossbar Switch Output Dividers and Drive Strength Control CLK1 (SS) CLK2 (No SS) CLK3 (SS) Cypress Semiconductor Corporation • 198 Champion Court wwwD.DocautamSheenett4#U: .0n0et1-12564 Rev. F • San Jose, CA 95134-1709 • 408-943-2600 Revised July 18, 2011 1 page CY25403/CY25423/CY25483 Absolute Maximum Conditions Parameter VDD VIN TS ESDHBM UL-94 MSL Description Condition Supply voltage for CY25403/CY25423/CY25483 – Input voltage for CY25403/CY25423/CY25483 Relative to VSS Temperature, Storage Non Functional ESD protection (human body model) JEDEC EIA/JESD22-A114-E Flammability rating V-0 at 1/8 in. Moisture sensitivity level SOIC package Recommended Operating Conditions Parameter VDD TAC TAI CLOAD tPU Description VDD operating voltage for CY25403/CY25423/CY25483 Commercial ambient temperature Industrial ambient temperature Maximum load capacitance Power-up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Min –0.5 –0.5 –65 2000 – –3 Max 4.5 VDD+0.5 +150 10 Unit V V °C Volts ppm – Min 2.25 0 –40 – 0.05 Typ Max Unit – 3.60 V – +70 °C -- +85 °C – 15 pF – 500 ms Document #: 001-12564 Rev. F Page 5 of 14 5 Page Acronyms DL DNU DUT EIA EMI ESD FAE FS JEDEC Acronym LVCMOS OE OSC PD PLL PPM SS SSC SSON Description drive level do not use device under test Electronic Industries Alliance electromagnetic interference electrostatic discharge field application engineer frequency select joint electron devices engineering council low voltage complementary metal oxide semiconductor output enable oscillator power-down phase-locked loop parts per million spread spectrum spread spectrum clock spread spectrum on CY25403/CY25423/CY25483 Document #: 001-12564 Rev. *F Page 11 of 14 11 Page

Páginas	Total 14 Páginas
PDF Descargar	[ Datasheet CY25423.PDF ]

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