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PDF CYDMX064A16 Data sheet ( Hoja de datos )
| Número de pieza | CYDMX064A16 | |
| Descripción | 16 K/8 K/4 K x 16 MoBL ADM 16 K/8 K/4 K x 16 MoBL ADM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
16 K/8 K/4 K × 16 MoBL® ADM
Asynchronous Dual-Port Static RAM
16 K/8 K/4 K × 16 MoBL® ADM Asynchronous Dual-Port Static RAM
Features
■ True dual-ported memory block that allow simultaneous
independent access
❐ One port with dedicated time multiplexed address and data
(ADM) interface
❐ One port configurable to standard SRAM or time multiplexed
address and data interface
■ 16 K/8 K/4 K × 16 memory configuration
■ High speed access
❐ 65 ns or 90 ns ADM interface
❐ 40 ns or 60 ns standard SRAM interface
■ Fully asynchronous operation
■ Port independent 1.8 V, 2.5 V, and 3.0 V IOs
Block Diagram
■ Ultra low operating power
❐ Active: ICC = 15 mA (typical) at 90 ns
❐ Active: ICC = 25 mA (typical) at 65 ns
❐ Standby: ISB3 = 2 A (typical)
■ Port independent power down
■ On-chip arbitration logic
■ Mailbox interrupt for port to port communication
■ Input Read and Output Drive registers
■ Upper byte and lower byte control
■ Small package: 6 × 6 mm, 100-ball Pb-free BGA
■ Industrial temperature range
SFEN#
IRR/ODR
IRR1-IRR0 [note 2]
ODR4-ODR0
I/OL15-I/OL8
I/OL7-I/OL0
ADV#L
UB#L
LB#L
Mux'ed
Address /
Data
I/O Control
DataL<15..0>
AddrL<13..0>
Dual Ported
Memory Array
16k/8k/4k x 16
DataR<15..0>
AddrR<13..0>
Mux'ed
Address/
Data
I/O Control
Address
Decode
Address
Decode
CS#L
OE#L
WE#L
BUSY#L
INT#L
Control Logic
CS#R
OE#R
WE#R
BUSY#R
INT#R
I/OR15-I/OR8
I/OR7-I/OR0
ADV#R
UB#R
LB#R
A13-A0 [note 1]
MSEL
Notes
1. A13-A0 for CYDMX256A16 and CYDMX256B16; A12-A0 for CYDMX128A16 and CYDMX128B16; and A11-A0 for CYDMX064A16 and CYDMX064B16.
2. IRR1 and IRR2 not available for CYDMX256A16 and CYDMX256B16.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-08090 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 2, 2011
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CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Standard SRAM Interface Read or Write Operation
This description is applicable to the right access port configured
as standard SRAM port. Read and write operations with
standard SRAM interface configuration is the same as the ADM
port except addresses are presented on the A bus. Operation is
controlled by CS#, OE#, and WE#. A read operation is issued
when WE# is asserted HIGH. A write operation is issued when
WE# is asserted LOW. The IO bus is the destination for read data
and the source for write data when the read operation is issued.
However, write data must be driven to IO when the write
operation is issued.
Byte Select Operation
The fundamental word size is 16 bits. Each word is broken up
into two 8-bit bytes. Each port has two active LOW byte enables:
UB# and LB#. Activating or deactivating the byte enables alters
the result of read and write operations to the port. During a write,
byte enable asserted HIGH inhibits the corresponding byte to be
updated in the addressed memory location. During a read, both
byte enables are inputs to the asynchronous output enable
control logic. When a byte enable is asserted HIGH, the
corresponding data byte is tri-stated. Subsequently, when the
byte enable is asserted LOW, the corresponding data byte is
driven with the read data.
Chip Select Operation
Each port has one active LOW chip select signal, CS#. CS# must
be asserted LOW for the port to be considered active. To issue
a valid read or write operation, the chip select input must be
asserted LOW throughout the read or write cycle. When CS# is
deasserted HIGH during a write, if tWRL, tSD, and tHD are not met,
the contents of the addressed location is not altered.
An automatic power down feature controlled by deactivating the
chip select (CS# HIGH) permits the on-chip circuitry of each port
to enter a very low standby power mode.
Output Enable Operation
Each port has one output enable signal, OE#. When OE# is
asserted HIGH, IO bus is tri-stated after tHZOE. When OE# is
asserted LOW, control of the IO bus is assumed by the
asynchronous output enable logic (the logic is controlled by
inputs WE#, CS#, UB#, and LB#).
Mailbox Interrupts
The upper two memory locations are used for message passing.
The highest memory location (0xFFF for CYDMX064A16 and
CYDMX064B16, 0x1FFF for CYDMX128A16 and CYDMX128B16,
and 0x3FFF for CYDMX256A16 and CYDMX256B16) is the
mailbox for the right port. The second highest memory location
(0xFFE for CYDMX064A16 and CYDMX064B16, 0x1FFE for
CYDMX128A16 and CYDMX128B16, and 0x3FFE for
CYDMX256A16 and CYDMX256B16) is the mailbox for the left
port. When one port writes to the opposite port’s mailbox, an
interrupt signal is generated to the opposite port. The interrupt
resets when the owner reads the contents of its own mailbox.
The message written to the mailbox is user defined.
Each port reads the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and resetting the interrupt to it.
On power up, both interrupts are set by default. An initialization
program must be run to reset the interrupts.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
Arbitration Logic
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 provide
on-chip arbitration to resolve simultaneous memory location
access (collision). If both ports’ CS# signals are asserted and an
address match occurs within each other, the busy logic deter-
mines which port has access. If tPS is violated, one of the two
ports gains permission to the location, but it is not predictable
which port gets the permission. BUSY# is asserted tBLA after an
address match or tBLC after CS# is taken LOW.
Input Read Register
The Input Read Register (IRR) feature is available only for
CYDMX128A16, CYDMX128B16, CYDMX064A16, and
CYDMX064B16 devices. When SFEN# = VIL, the IRR captures
the status of two external devices connected to the Input Read
pins (IRR0 and IRR1) to address location 0x0000. Address
0x0000 is not available for standard memory accesses when
SFEN# = VIL. When SFEN# = VIH, address 0x0000 is available
for normal memory accesses. Either port accesses the contents
of IRR with normal read operation from address 0x0000. During
reads from the IRR, IO<1:0> are valid bits and IO<15:2> are
don’t care. The IRR inputs are 1.8 V and 2.5 V LVCMOS or 3.0 V
LVTTL, depending on the core voltage supply (VCC).
Output Drive Register
The Output Drive Register (ODR) determines the state of up to
five external binary state devices by providing a path to VSS for
the external circuit. These outputs are open drain. The five
external devices operates at different voltages
(1.5 V VDDIO 3.5 V) but the combined current cannot exceed
40 mA (8 mA maximum for each external device). The status of
the ODR bits are set using standard write accesses from either
port to address 0x0001 with a ‘1’ corresponding to on and ‘0’
corresponding to off. The status of the ODR bits are read with a
normal read access to address 0x0001. When SFEN# = VIL, the
ODR is active and address 0x0001 is not available for memory
accesses. When SFEN# = VIH, the ODR is inactive and address
0x0001 is used for standard accesses. During reads and writes
to ODR, IO<4:0> are valid and IO<15:5> are don’t care.
Document #: 001-08090 Rev. *G
Page 5 of 25
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CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Electrical Characteristics for 3.0 V
Over the Operating Range
VOH
VOL
VOL
ODR
VIH
VIL
IOZ
ICEX
ODR
IIX
ICC
ISB1
ISB2
ISB3
ISB4
CYDMX256A16
CYDMX128A16
Description
P1 IO P2 IO
Voltage Voltage
Min
Output HIGH Voltage (IOH = –2 mA) 3.0 V (any port)
Output LOW Voltage (IOL = 2 mA
3.0 V (any port)
ODR Output LOW Voltage (IOL = 8 mA 3.0 V (any port)
2.1
–
–
–65
Typ
–
–
–
Max
–
0.4
0.2
CYDMX256B16
CYDMX128B16
CYDMX064B16
–65
Min Typ Max
2.1 – –
– – 0.4
– – 0.2
CYDMX256A16
CYDMX128A16
CYDMX064A16
–90
Unit
Min Typ Max
2.1 – – V
– – 0.4 V
– – 0.2 V
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
ODR Output Leakage Current.
VOUT = VCC
Input Leakage Current
Operating Current
(VCC = Max, IOUT = 0 mA)
Outputs Disabled
Standby Current
(Both Ports TTL Level)
CE#L and CE#R VCC – 0.2,
f = fMAX
Standby Current
(One Port TTL Level)
CE#L or CE#R VIH, f = fMAX
3.0 V (any port) 2.0 – VDDIO 2.0
+ 0.2
3.0 V (any port) –0.2 – 0.7 –0.2
3.0 V 3.0 V –1 – 1 –1
3.0 V 3.0 V –1 – 1 –1
3.0 V 3.0 V –1 – 1 –1
Ind. 3.0 V 3.0 V – 49 70 –
Ind. 3.0 V 3.0 V
Ind. 3.0 V 3.0 V
Ind. 3.0 V 3.0 V
Ind. 3.0 V 3.0 V
7 10
28 40
68
28 40
– VDDIO 2.0
+ 0.2
– 0.7 –0.2
– 1 –1
– 1 –1
– 1 –1
49 70 –
7 10
28 40
68
28 40
– VDDIO V
+ 0.2
– 0.7 V
– 1 A
– 1 A
– 1 A
42 60 mA
7 10 A
25 35 mA
6 8 A
25 35 mA
Capacitance[22]
CIN
COUT
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = 3.0 V
Max
9
10
Unit
pF
pF
Note
22. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-08090 Rev. *G
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| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet CYDMX064A16.PDF ] | |
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