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PDF CY62187EV30 Data sheet ( Hoja de datos )
| Número de pieza | CY62187EV30 | |
| Descripción | 64-Mbit (4 M x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62187EV30 MoBL®
64-Mbit (4 M × 16) Static RAM
64-Mbit (4 M × 16) Static RAM
Features
■ Very high speed
❐ 55 ns
■ Wide voltage range
❐ 2.2 V to 3.7 V
■ Ultra low standby power
❐ Typical standby current: 8 μA
❐ Maximum standby current: 48 μA
■ Ultra low active power
❐ Typical active current: 7.5 mA at f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Available in Pb-free 48-ball FBGA package
Functional Description
The CY62187EV30 is a high performance CMOS static RAM
organized as 4 M words by 16-bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 99 percent when addresses are not toggling.
The device can also be put into standby mode when deselected
(CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The
input and output pins (I/O0 through I/O15) are placed in a high
impedance state when: deselected (CE1HIGH or CE2 LOW),
outputs are disabled (OE HIGH), both Byte High Enable and Byte
Low Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE1 LOW, CE2 HIGH and WE LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A21). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A21).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See the Truth Table on page
9 for a complete description of read and write modes.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4NUu.nmebt er: 001-48998 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 14, 2011
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CY62187EV30 MoBL®
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied .......................................... –55 °C to +125 °C
Supply Voltage to Ground
Potential........................................ –0.3 V to VCC(max) + 0.3 V
DC Voltage Applied to Outputs
in High Z State [2, 3]....................... –0.3 V to VCC(max) + 0.3 V
DC Input Voltage [2, 3] .................. –0.3 V to VCC (max) + 0.3 V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch Up Current .................................................... > 200 mA
Operating Range
Device
Range
Ambient
Temperature
VCC[4]
CY62187EV30LL Industrial –40 °C to +85 °C 2.2 V to 3.7 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
VOH Output HIGH voltage
VOL Output LOW voltage
VIH Input HIGH voltage
VIL Input LOW voltage
IIX
IOZ
ICC
ISB2 [7]
Input leakage current
Output leakage current
VCC operating supply
current
Automatic CE
power down
current—CMOS inputs
Capacitance
Parameter[8]
Description
CIN
COUT
Input capacitance
Output capacitance
Test Conditions
2.2 V < VCC < 2.7 V IOH = –0.1 mA
2.7 V < VCC < 3.7 V IOH = –1.0 mA
2.2 V < VCC < 2.7 V IOL = 0.1 mA
2.7 V < VCC < 3.7 V IOL = 2.1 mA
2.2 V < VCC < 2.7 V
2.7 V < VCC < 3.7 V
2.2 V< VCC < 2.7 V
2.7 V < VCC < 3.7 V
GND < VI < VCC
GND < VO < VCC, output disabled
f = fMax = 1/tRC
f = 1 MHz
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0,
VCC = 3.7 V
Min
2.0
2.4
–
–
1.8
2.2
–0.3
–0.3
–1
–1
–
–
55 ns
Typ[5]
Max
––
––
– 0.4
– 0.4
– VCC + 0.3 V
– VCC + 0.3 V
– 0.6
– 0.8[6]
– +1
– +1
45 55
7.5 9
Unit
V
V
V
V
V
V
V
V
μA
μA
mA
mA
–8
48 μA
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max Unit
25 pF
35 pF
Notes
2. VIL(min) = –2.0V for pulse durations less than 20 ns.
3. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
4. Full Device AC operation assumes a 100 μs ramp time from 0 to VCC (min) and 200 μs wait time after VCC stabilization.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
6. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions input LOW Voltage applied to the device must not be higher than 0.7 V.
7. Chip enables (CE1 and CE2) and Byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-48998 Rev. *F
Page 5 of 15
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Truth Table
CE1
H
X[27]
X[27]
L
L
CE2
X[27]
L
X[27]
H
H
WE
X
X
X
H
H
L HH
LHL
LHL
LHL
L HH
L HH
L HH
OE BHE BLE
Inputs Outputs
X X[27] X[27] High Z
X X[27] X[27] High Z
X H H High Z
L L L Data Out (I/O0–I/O15)
L H L High Z (I/O8–I/O15);
Data Out (I/O0–I/O7)
L L H Data Out (I/O8–I/O15);
High Z (I/O0–I/O7)
X L L Data In (I/O0–I/O15)
X H L High Z (I/O8–I/O15);
Data In (I/O0–I/O7)
X L H Data In (I/O8–I/O15);
High Z (I/O0–I/O7)
H L H High Z
H H L High Z
H L L High Z
CY62187EV30 MoBL®
Mode
Deselect/Power Down
Deselect/Power Down
Deselect/Power Down
Read
Read
Read
Write
Write
Write
Output Disabled
Output Disabled
Output Disabled
Power
Standby (ISB)
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Note
27. The ‘X’ (Don’t care) state for the chip enables and byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
Document Number: 001-48998 Rev. *F
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| PDF Descargar | [ Datasheet CY62187EV30.PDF ] | |
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