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PDF CY62177EV30 Data sheet ( Hoja de datos )
| Número de pieza | CY62177EV30 | |
| Descripción | 32-Mbit (2M x 16) Static | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62177EV30 MoBL®
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
Features
■ Thin small outline package (TSOP) I configurable as 2 M × 16
or as 4 M x 8 static RAM (SRAM)
■ Very high speed
❐ 55 ns
■ Wide voltage range
❐ 2.2 V to 3.7 V
■ Ultra low standby power
❐ Typical standby current: 3 A
❐ Maximum standby current: 25 A
■ Ultra low active power
❐ Typical active current: 4.5 mA at f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE Features
■ Automatic power down when deselected
■ Complementary Metal Oxide Semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 48-ball TSOP I package
Logic Block Diagram
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
2M × 16
RAM Array
Functional Description
The CY62177EV30 is a high performance CMOS static RAM
organized as 2 M words by 16 bits and 4 M words by 8 bits. This
device features advanced circuit design to provide ultra low
active current. It is ideal for providing More Battery Life
(MoBL®) in portable applications such as cellular telephones.
The device also has an automatic power down feature that
significantly reduces power consumption by 99 percent when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or both
BHE and BLE are HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when: deselected
(CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE
LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A20). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written to the location specified on the
address pins (A0 through A20). To read from the device, take
Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins appear on I/O0 to I/O7. If Byte High
Enable (BHE) is LOW, then data from memory appears on I/O8
to I/O15. See the Truth Table on page 10 for a complete
description of read and write modes.
Pin #13 of the 48 TSOP I package is an DNU pin that must be
left floating at all times to ensure proper application.
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power-Down
Circuit
BHE
BLE
BYTE
BHE
WE
OE
BLE
CE2
CE1
CE2
CE1
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4NUu.nmebt er: 001-09880 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 29, 2011
1 page  
CY62177EV30 MoBL®
Thermal Resistance
Parameter[12]
JA
Description
Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch, 2-layer
printed circuit board
TSOPI
44.66
12.12
Unit
C/W
C/W
VCC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Figure 2. AC Test Loads and Waveforms
R1
R2
VCC
GND
10%
Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
V
Table 1. AC Test Loads
Parameter
R1
R2
RTH
VTH
2.5 V
16667
15385
8000
1.20
3.3 V
1103
1554
645
1.75
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
VDR
ICCDR [14]
tCDR[12]
tR[15]
VCC for data retention
Data retention current
Chip deselect to data
retention time
VCC = 1.5 V, CE1 > VCC – 0.2 V or CE2 < 0.2 V, or
(BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V or
VIN < 0.2 V
Operation recovery time
VCC
CE1 or
BHE.BLE
or
CE2
Figure 3. Data Retention Waveform [16]
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.5 V
Unit
V
Min Typ[13] Max
1.5 – –
– – 17
0 ––
55 – –
VCC(min)
tR
Unit
V
A
ns
ns
Notes
12. Tested initially and after any design or process changes that may affect these parameters.
13. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
14. Chip enables (CE1 and CE2) and Byte Enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
15. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
16. BHE.BLE is the AND of both BHE and BLE. Chip is deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-09880 Rev. *H
Page 5 of 15
5 Page 
CY62177EV30 MoBL®
Ordering Information
Speed
(ns)
Ordering Code
55 CY62177EV30LL-55ZXI
Package
Diagram
Package Type
51-85183 48-pin TSOP I (12 × 18.4 × 1 mm) Pb-free
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 7 7 E V30 LL - 55 Z X I
Temperature Grade:
I = Industrial
X = Pb-free
Package Type:
Z = 48-pin TSOP I
Speed Grade: 55 ns
Low Power
Voltage Range: V30 = 3 V (typical)
Process Technology: E = 90 nm
Bus Width = × 16
Density = 32-Mbit
621 = MoBL SRAM family
Company ID: CY = Cypress
Operating
Range
Industrial
Document Number: 001-09880 Rev. *H
Page 11 of 15
11 Page | ||
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| PDF Descargar | [ Datasheet CY62177EV30.PDF ] | |
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